Page 48 - Chip Scale Review_March-April_2024-digital

than 80%. Again, this is because of correlate very well (more than 95%
the thinner packaging enabled by
HCB; additionally, there are no Cu- resistance fabricated with the HCB
pillar with solder cap and underfill/ is 15~30% less than that with the
NCF structures, which increase the
thermal resistance.
Figure 5 shows the simulation and
measurement results of the 16H HBM
package with the HCB and TCB-NCF
methods. It can be seen that: 1) the
simulation and measurement results
46 Chip Scale Review March • April • 2024
46
density and better thermal dissipation
matched); and 2) the stack thermal
TCB-NCF.
SK Hynix’s hybrid bonding for HBM the solder-bumped mass reflow method
During IEEE/ECTC 2023, SK Hynix
presented at least one paper on a
chip-to-wafer (C2W) hybrid bonding
interconnect technology for higher
P However, with hybrid bonding, the
RoHS
[ChipScaleReview.com]
of HBM [13]. The paper’s focus is on
the demonstration of a 8Hi-HBI (hybrid
bonding intercon nect) with C2W
multi-stack HBM as shown in Figure
6. It can be seen that comparing with
(chapter 1 of [8]), the thickness of the
HBM package can be reduced by 15%
with the Cu-Cu bumpless HBI method.
Plasma treatment is a key process
step for preparing the bonding surface
that makes oxide bonding at room
temperature with CMP in HBI. The
authors consider three different kinds
of plasma conditions, namely, A, B,
and C. Figure 7 shows the bonding
s t r e ng t h a nd s c a n n i ng a c ou s t ic
microscopy (SAM) images of samples
under plasma conditions A, B, and C
after end-of-line and reliability testing.
It can be seen that plasma condition
B yields the highest bonding strength
that is measured by the Maszara test
in wafer-to-wafer base. The annealing
temperature is 200ºC. There is no void
after the end of line. However, there
are voids after the reliability test.
Thermal resistances of MR+MUF
(8Hi) and HBI (8Hi) structures with
different pad densities are shown in
Figure 8. It can be seen that: 1) for the
same pad density (20%), the thermal
resistance of the HBI (8Hi) is 22%
lower than that of the MR+MUF (8Hi);
and 2) the thermal resistance of the
HBI (8Hi) (with 8% pad density) is
13% lower than that of the MR+MUF
(8Hi) (with 20% bump density).
Micron’s hybrid bonding for HBM
D u r i n g E C T C 20 2 3 , M i c r o n
publ ishe d at lea st one pape r on
critical challenges with copper hybrid
bonding for C2W memory stacking
[14]. Figure 9a shows a conventional
stacking of TSV-dies with µbumps
solder reflow method for HBM. The
µbump pitch can go down to 20µm.
Cu pad pitch can easily go down
t o 10 µ m a n d t h e r e i s n o bu m p,
i.e., bumpless as shown in Figure
9b. Figure 9c shows the electron
back s c at t er d i f f r ac t ion ( EBSD)
across the bonding interface where
two Cu pads are joined together. Due
to Cu-to-Cu diffusion, these two Cu
pads become one with the Cu crystal