Page 47 - Chip Scale Review_March-April_2024-digital

Figure 3: Thermal resistance in 16H HBM structure:
conventional flip chip vs. HCB. SOURCES: [7,11]
One of the challenges of HBM is Figure 4: Joint thermal resistance of MR-MUF, TCB-NCF, and HCB. SOURCES: [7,12]
thermal management. Because there
are no gaps between the chips, the
vertical thermal resistance of the 16H
HBM with the HCB is 20% lower than
that for the flip-chip case with gaps
for the µbumps and underfill (NCF) as
shown in Figure 3 [11].
At ECTC 2023, Samsung published
another paper on thermal improvement
of HBM with joint thermal resistance
reduction for scaling 12 stacks and
beyond [12]. The authors stated that
there are two factors affecting the
HBM temperature: 1) internally (HBM
itself ), thermal resistance, power
magnitude and map (distribution),
and temperature sensor location;
and 2) externally (system), cooling
performance, graphics processing unit
(GPU), application-specific integrated
circuit (ASIC), central processing unit
(CPU) power, and system-in-package
(SiP) structure. In [12] their focus
is on the inside of HBM and dealing
with thermal resistance improvement Figure 5: Measured and simulated stack thermal resistance of HBM with TCB and HCB. SOURCES: [7,12]
methods such as HCB.
Figure 4 shows the simulation
results on joint thermal resistance
with arbitrary units (A.U.) vs. joint
gap thickness for mass reflow (MR)-
molded underfill (MUF), TCB-NCF,
and HCB. MR-MUF and TCB-NCF
have been discussed in chapter 1 of
[8]. It can be seen from Figure 4
that: 1) the joint thermal resistance
is the lowest for HCB; 2) the joint
ther mal resistance is highest for
MR-MUF; 3) the reduction of joint
thermal resistance from MR-MUF
to TCB -NCF is 35%; a nd 4) t he
reduction of joint thermal resistance
f r om M R- M U F t o HC B i s mor e Figure 6: Comparison between a solder-bumped flip chip and hybrid bonding interconnect. SOURCES: [7,13]

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