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copper pilla r. T he 256 cha n nels Hybrid bonding: A solution for bonding, which require temperature and
of the OPA are wire bonded to a heterogeneity pressure, or additional materials such as
printed circuit board (PCB) and an Hybr id bond i ng is a mat u r i ng polymer, respectively, to ensure contact
8-channel fiber array is connected to technology in advanced fabs that between the two surfaces. Following
deliver the laser beam. The system is essential to the emergence of 3D stringent surface preparation—i.e.,
is fully functional and complies with devices. This technology is similar to topography and cleanliness—direct
advanced driver assistance systems direct bonding, but is applied to mixed bonding is spontaneous, requiring no
(A DAS) specif ications for beam Cu/dielectric surfaces to create an external loading.
scanning angles, divergence and power electrical interconnection between two HB is par ticularly suitable for
consumption [11]. parts. Direct bonding is quite distinct interconnection densities with pitches
from thermocompression and adhesive from 0.5µm to 10µm. The race to achieve
higher interconnection densities is the
main driver on the HB development
roadmap for HPC or imaging applications
[12]. However, HB is also more reliable
and results in a thinner total stack
compared to micro-bumps, which are
used in automotive applications and
high-bandwidth memory applications.
HB has matured enough to have
entered mass production, especially
for stacked image sensors in its wafer-
to-wafer version. Devices with two-
die stacks are available on the market,
and advanced research on three-die
stacks are advancing well. Die-to-wafer
(DTW) hybrid bonding will dramatically
enhance designer creativity as several
a dva nced t e ch nolog y nodes a nd
substrates can be assembled on a single
interposer to produce heterogeneous 3D
(Figure 5).
For future research on HB, the
development of low-temperat u re
processes will be key to addressing
technologies with a low thermal budget.
For example, SA is being explored, as are
horizontal die-to-die interconnections by
HB [13]. In the latter context, interposer
or bridges should make it possible to
overcome stepper limitations.
3D sequential integration:
Optimizing 3D contact densities
The strategy adopted at CEA-Leti to
introduce iBEOL between sequentially
stacked tiers introduced the following
new challenges: 1) a limitation of the
top CMOS field-effect transistor (FET)
thermal budget process to 500°C, and
2) the need to ensure a safe return
to only front end of line (FEOL)
contamination when processing the top
transistor. Figure 6 shows the recent
demonstration of one such integration
[14]. Above a standard industrial
28n m f ully- depleted silicon- on-
insulator (FD-SOI) platform including
four Cu/ultra low-k (ULK) dielectric
metal levels, the top CMOS device
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40 Chip Scale Review March • April • 2024 [ChipScaleReview.com]
