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Figure 17: Shadow Moiré measurement of the assembled RDL interposer on an organic substrate.
in the stitched str ucture and low Ching, and Jacob Jordon Soh for their technology,” IEEE 73rd ECTC
leakage current in the intra-layer RDL. support in the chiplets assembly, underfill (2023), pp. 893-898.
A daisy chain connectivity test was and wafer-level molding process. 4. K . Mu r a i , e t a l ., “ S t u d y of
also performed for the 12 chiplets, Portions of this article were presented fabrication and reliability for the
demonstrating good connectivity with at the IEEE/EPTC2023 conference; the extremely large 2.5D advanced
the RDL layer. Shadow Moiré warpage article was edited for publication in Chip package,” IEEE 73rd ECTC (2023),
measurement was carried out on the Scale Review. pp. 899-906.
fabricated RDL interposer package 5. S. Miki, et al., “Development of
revealed significant variations during References 2.3D high density organic package
temperature changes, prompting the 1. K. Sakuma, et al., “Heterogeneous using low temperature bonding
implementation of a TCB process integration on organic interposer process with Sn-Bi solder,” IEEE
to mitigate warpage issues during substrate with fine-pitch RDL and 69th ECTC (2019), pp. 1599-1604.
assembly of the RDL interposer onto 40 micron pitch micro-bumps,” 6. V. S. Rao, et al., “Development of
an organic substrate. IEEE 73rd Electronic Components high density fan out wafer level
and Tech. Conf. (ECTC) (2023) pp. package (HD FOWLP) with multi-
Acknowledgements 872-877. layer fine pitch RDL for mobile
This research was supported by the 2. Y. Lin, et al., “Multilayer RDL applications,” IEEE 66th ECTC
Agency for Science, Technology and interposer for heterogeneous device (2016), pp. 1522-1529.
Research (A*STAR) under Centre of and module integration,” IEEE 69th
Excellence in Advanced Packaging 3.0 ECTC (2019), pp. 931-936.
(Grant No I2101E0008). The authors 3. I. Lee, et al., “Extremely large
would like to thank their colleagues: 3.5D heterogeneous integration
Sharon Lim Pei Siang, Eva Wai Leong for the next-generation packaging

Biographies
Soon We Ho is Principal Research Engineer at the Institute of Microelectronics, A*STAR (Agency for
Science, Technology and Research), Singapore. He obtained his BEngg degree in Material Engineering from
Nanyang Technological U., Singapore in 2005. Since 2006, he has dedicated his work to advancing packaging
development at the Institute of Microelectronics (IME), Singapore. His primary research interests lie in
heterogeneous integration, with a specific focus on fan-out wafer-level package and through-silicon via (TSV)
technology. Email hosw@ime.a-star.edu.sg
Siew Boon Soh is a Senior Research Engineer at the Institute of Microelectronics, A*STAR (Agency for Science,
Technology and Research), Singapore. She brings with her a wealth of knowledge in testing and process development for
advanced packaging, acquired during her tenure at Advanced Micro Devices (AMD) in Singapore, and Nepes Pte Ltd. Her
current research focus is on heterogeneous integration, with an emphasis on fan-out wafer-level packaging and through-silicon
via (TSV) technology.

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