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Heterogeneous packaging: Optimizing performance

and power consumption

By Jean-Charles Souriau [CEA-Leti]
B ecause of the increasing To r e d u c e t h e d i e - t o - w a f e r disruptive approach to HPC: optical

costs of advanced nodes
a nd t he dif f icult ies of (DTW) interconnect pitch, leading network-on-chip (ONoC) technology.
Photons (light) have the potential to
m ic roele ct ron ics ma nufact u re r s
shrinking analog and circuit input- consider that direct hybrid bonding deliver fast on-chip communication
output signals (IOs), alternatives to ( H B), usi ng m i xed copper/oxide for HPC, with increased bandwidth
single-die architectures are becoming interfaces, will be essential for the and reduced power consumption [5].
mainstream. Chiplet-based systems success of future memory stacks, HPC, The main technological challenges
using 3D technologies are compatible and to support the continued application faced by our architectural vision of
with scalable modular architectures, of Moore’s Law. Het e roge ne ou s an ONoC approach to chiplets were:
and with technology partitioning based 3D integration has been identified 1) a scalable, low-profile interface
on reusable intellectual property (IP) as a way to increase functionality between the chiplets and network; 2)
blocks. Moreover, 3D interconnects per unit area by optimizing space decentralized routing to reduce data
increase chip-to-chip bandwidth and in the x, y and z directions. For movement within the system; 3) thermal
limit overall power consumption. over 10 years, CEA-Leti has been management compatible with optical
Industries across the whole range part of the French public Nanoelec communications; and 4) maintaining
from automotive to high-performance Technological Research Instit ute individual chiplet performance in
computing (HPC) will soon be relying on ecosystem, gathering 22 partners from multiple-chiplet integrations.
advanced packaging to deliver simpler, academic research institutions and B y t a c k l i n g t h e i s s u e s n o t e d
faster, and cheaper chip designs that industry [2]. Within this framework, above, we successfully co-integrated
integrate more functions while offering to offer advanced packaging and HB 3D interconnections and photonic
greater performance and versatility. solutions, we have teamed up with devices using a newly demonstrated
The chiplet-on-interposer concept equipment manufacturers (SET, EVG, approach to form 10µm diameter by
involves integrating a multiplicity of etc.) and adapted specific bonding 100µm high TSVs through copper
chips on the same silicon platform; processes —f rom pick-a nd-pla ce metallization inside a photonic chip
it contrasts with large monolithic technology to self-assembly (SA)—to [6]. Thermal insulation was improved
systems-on-chip (SoCs) platforms. improve yield and alignment accuracy. by etching 40µm diameter backside
The active interposer extends this Today, we can bond chips from 1mm² cavities beneath the optical micro-
concept by adding smart functions × 1mm² to 10mm² × 10mm² by HB rings, leading to a 70% reduction in the
at t he i nt e r p ose r level, s uch a s with interconnect pitches from 10μm power required to tune the micro-rings.
c o m p l e me n t a r y me t a l - o x i d e - to less than 5μm [3]. In addition, Moreover, we have shown efficient
semiconductor (CMOS) components. die spacing can be as low as 40μm. thermomechanical stress management
The inter poser, thereby, becomes Current developments are focused on of t he t h i n ne d 10 0 µ m phot o n ic
more than a simple interconnection multi-stack DTW processes. We have interposer for assembly processes [7].
platform; it provides the foundation demonstrated that signals and power 3D sequential integration makes it
for analog and low-power digital and supply from top-die circuits can be possible to achieve the best possible 3D
photonic functions and increased communicated to a substrate using contact densities between stacked tiers
3D communication, especially with through-silicon vias (TSVs) [4]. We (<100nm pitch). This integration is
network-on-chip architectures. are also working on new integration attracting strong interest for more-than-
In 2019, CEA-Leti and CEA-List technologies such as SA. The advances Moore applications, such as CMOS
presented the f irst CMOS active m a d e p r ov id e h ig he r a l ig n me nt image sensors with smart, scaled
i nter poser mea su red on silicon, performance (+/-200nm) and increased pixels, or mixed-signal applications
i nt e g r a t i n g p owe r m a n a ge m e nt throughput (thousands of dies/h). where low-voltage analog and digital
and dist r ibuted intercon nects to Another key area of research relates to dev ice s occupy se pa r at e levels,
create an innovative scalable cache- optimization of the temperature of the thereby allowing their independent
coherent memory hierarchy. In this HB process, with the aim of preserving optimization. The introduction of
demonstration, six 28nm FD-SOI memory or active device performance. intermediate back end of line (iBEOL)
chiplets were 3D-stacked onto an active To further improve data transmission between the stacked transistors will
interposer in a 65nm process, to create d u r i n g c o m m u n i c a t i o n , we a r e add to the variety of applications that
a total of 96 cores [1]. contributing to the development of a this technology can address.

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