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fabrication of top-quality devices at Acknowledgment cav it ie s for t he r m al t u n i ng
low temperatures without limiting This work was partly supported by optimization of silicon r ing
performance compared to traditional the French National program “IRT resonators,” IEEE 71st ECTC
high-temperature CMOS devices. This Nanoelec, n° ANR-10-AIRT-05 and (2 0 21) p p. 16 67-1672 , d o i :
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n 780548 (3D-MUSE). This work is in the development of high-
Advanced packaging: Toward a part of the IPCEI Microelectronics and density TSV for 3-layers CMOS
European 3D strategy Connectivity and was supported by the i m a ge s e n s o r s ,” I E E E 73r d
Future HPC, artificial intelligence (AI), French Public Authorities within the ECTC, Orlando, FL, USA, 2023,
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Biography
Jean-Charles Souriau is a scientist leader in the field of wafer-level packaging for more than 20 years at CEA-
Leti, Grenoble, France. He has worked at the Electronics and Information Technology Laboratory, French
Atomic Energy Commission, Micro and Nanotechnologies Campus. He is chair of the French chapter of the
IEEE Electronics Packaging Society and Technical Director of IMAPS France. He received the PhD degree in
physics from the U. of Grenoble, France in 1993. Email jean-charles.souriau@cea.fr

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