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monitored and reviewed to positively impact design improvements
        as a process plan of record. This shows the importance of design for
        manufacturability and the critical component for feedback. All of
        these inputs combined show the complexities and critical interface
        loop between designs for manufacturability purposes.

        Summary
          To keep unwanted defects from escaping, sound practices
        of design for manufacturing should be used and implemented
        within all design centers. As noted, dicing streets are becoming
        more complex with increasing device functionality needs, and
        this interacts with die size reductions and the drive for smaller
        dicing streets while still meeting end user requirements.
          There is not one common direction or decision that can
        be made on what is in the dicing street any longer, as it
        really is driven by far too many factors that enable negative  Figure 7: Silicon interaction to chipping.
        results from the dicing standpoint. The key is having a solid
        manufacturing review process and feedback loop to the design




















                                                            Figure 8: Dicing assembly interactions.
                                                            teams so that design for manufacturability based on lessons
                                                            learned is incorporated for long term success.
                                                              The best case is to design for the worst case technology
                                                            challenges and enable the best process design up front
                                                            and design process capabilities accordingly. Formulating
                                                            lessons learned and utilizing a test chip strategy early with
                                                            new silicon releases will eliminate unwanted surprises as
                                                            complexities grow and continue to grow over the life of a
                                                            silicon node or platform.

                                                            Reference
                                                             1.  M. Todd Wyant, “Wafer chip-scale package cost reductions,”
                                                                Mar/Apr 2015, Chip Scale Review, Vol. 19 No. 2, pp. 54-56.







                       Biography
                         M. Todd Wyant is Sr. Member of the Technical Staff, Semiconductor Packaging Organization, Dallas, TX. His
                       career spans 25+ years and includes roles at Chrysler Corp., General Motors, and Delphi Electronics before he
                       joined TI. He earned a BSME in Mechanical Engineering from Purdue U. and a Six Sigma Black Belt from AIT.
                       Email m-wyant@ti.com





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