Page 45 - Chip Scale Review_September-October_2023-digital

Mitigating the thermal bottleneck in advanced interconnects

By Zsolt Tőkei, Herman Oprins, Melina Lofrano, Xinyue Chang [imec]
T he back-end-of-line (BEOL) logic cells dissipate around 10W/ The need for an accurate predictive

2
is a complex wiring scheme
that distributes clock and m m , and some of the generated framework
Traditionally, ther mal analysis
h e a t i s d i s s i p a t e d t o wa r d s t h e
other signals, provides power and neighboring BEOL [1,2]. On top of of FEOL and BEOL is performed
ground, and transfers electrical signals that, the currents that run through the separately using simplified models,
from one transistor to another. It is interconnects for either power delivery and only the impact of the transistor on
organized in different metal layers or signal distribution also warm up the first metal layer (M1) is considered.
containing local (M x ), intermediate the conductors, a phenomenon known But this approach is becoming too
(M y ), and (semi-)global interconnect as Joule heating. This worsens with narrow. The concern is fueled by
wi res (M z ). T he tot al nu mber of each technology node due to a scaling- emerging innovations that are expected
layers can be as many as 15, while the induced rise in the electrical resistivity to go against thermal improvement.
typical number of M x layers ranges of the interconnect metal lines and Think about the introduction of air
between 3 and 6. Each layer contains vias. The requirements for ever higher gaps as alter native dielectrics to
unidirectional metal lines, organized current densities and the poor thermal improve RC delay or a further increase
in regular tracks and sur rounded conductivity of the low-k dielectrics in the number of BEOL layers. Also,
by intermetal dielectrics. They are add to the problem. for 3D technologies, the BEOL might
interconnected vertically using via become the dominant contributor to the
structures that are filled with metal.
As dimensional scaling in the front-
end-of-line (FEOL) continues, BEOL
dimensions are also being reduced –
leading to ever smaller metal pitches
and reduced cross-sectional areas of
the wires. Routing congestion and
growing RC delay (resulting from
an increased resistance-capacitance
product (RC)) have become well-
k now n b o t t l e n e c k s f o r f u r t h e r
interconnect scaling.
The chip industry, however, has
for some time been concerned about
another phenomenon: an increase in
the BEOL’s thermal resistance and,
with it, the heating up of the metal
lines. This temperature increase can
dramatically affect the reliability of
the integrated circuits because the
reliability degradation of both the
BEOL (related to electromigration and
stress migration) and the FEOL (related
to, e.g., negative bias temperature
instability) is accelerated at high
temperatures.
The main sources for heating are
the active parts in the FEOL, the E-Tec Interconnect AG, Mr. Pablo Rodriguez, Lengnau Switzerland
Phone : +41 32 654 15 50, E-mail: p.rodriguez@e-tec.com
transistors, which dissipate energy
during their operation. Nowadays,

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