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Summary with the logic cells in the front-end-of- copy should go to the following link and
As dimensional scaling continues, line (FEOL) and boundary conditions complete the contact form: https://www.
the heating of the interconnects in the from packaging technologies. We imec-int.com/en/connect-with-us
chip’s back-end-of-line (BEOL) has discussed the model and its added value.
become a growing concern because it Valuable insights were presented, such References
can compromise the chip’s reliability. as the dominant contribution of low-k 1. M. Lofrano, et al., “Towards accurate
Howeve r, a c c u r at e mo del s w it h dielectrics and via layers to the BEOL’s temperature prediction in BEOL for
satisfactory spatial resolution and, at the thermal resistance. reliability assessment,” IRPS 2023
same time, reasonable computation time (Invited).
are scarce. We have presented a modeling Acknowledgment 2. X. Chang et al., “Calibrated fast
framework that accurately predicts The results presented in this article are thermal calculation and experimental
heat dissipation in advanced BEOL described in more detail in the following characterization of advanced BEOL
structures, considering the coupling papers. Those interested in receiving a stacks,” IEEE IITC/MAM 2023.
Biographies
Zsolt Tőkei is an imec Fellow and Program Director of nano-interconnects at imec, Leuven, Belgium. He
joined imec in 1999 and has held various technical positions in the organization. He earned an MS in Physics
from the U. Kossuth in Debrecen, Hungary. In the framework of a co-directed thesis between the Hungarian
U. Kossuth and the French U. Aix Marseille-III, he obtained his PhD in Physics and Materials Science.
Email: Zsolt.Tokei@imec.be
Herman Oprins is a Principal Member of technical staff and R&D Team Leader at imec, Leuven, Belgium,
where he leads the thermal modeling and characterization team. He joined imec in 2003, where he has been involved in thermal
experimental characterization, thermal modeling, and thermal management solutions ranging from device level, over chip level,
to the system level. He holds a MSc and PhD in Mechanical Engineering from the KU Leuven, Belgium.
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48 Chip Scale Review September • October • 2023 [ChipScaleReview.com]