Page 49 - Chip Scale Review_September-October_2023-digital

Figure 6: Three IC package options: a) over-molded package with natural convection; b) over-molded with metal lid frame package with natural convection; and c)
bare die package with forced cooling. Thermal resistances obtained from experimental characterization are added.

words, this cooling solution results
in a large thermal resistance for the
FEOL and the BEOL self-heating.
T he se cond a nd t h i rd sce n a r ios
improve the thermal path towards
the top resulting in a 40 percent and
90 percent temperature reduction,
respectively, for the same FEOL
power, while the BEOL self-heating
only reduces slightly.

A valuable tool for STCO
A s e x p l a i n e d a b o v e , e a c h
presented model can be deployed
for specific use cases, depending
on the dimensional scale of interest.
For example, the FEM model can be
applied to simplified BEOL stacks to
investigate thermal aspects of more
advanced met allizat ion schemes
at the local level, such as semi-
damascene. Also, alternative routing
and power delivery schemes—such
as backside power deliver y— can
be assessed by feeding in different
p a c k a g e c o n f i g u r a t i o n s i n t h e
package model.
Ultimately, mitigating the thermal
bottleneck in the chip’s BEOL will
bring system performance benefits
for targeted applications. As such,
the models proposed in this work will
help identify the right technology
ingredients that can unlock major
system scaling bottlenecks. They
w i l l p r ov id e va lu a ble i nput for
RoHS
imec’s 3D and design-technology P
co-optimization (DTCO) work and,
eventually, for the system-technology
co-optimization (STCO) that starts
from system application needs.

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