Page 41 - Chip Scale Review_September-October_2023-digital

only 4 circuits per carrier and 60-second
wafer + tooling exchange time on a
single-wafer table system up to a 93%
advantage when there are 1,024 circuits
on a carrier and an exchange time of only
15 seconds.
Impact of the number of die types
and counts per circuit. The impact of
the number of unique die types per circuit
and the quantity of each die type on the
relative throughput of each solution type
was also analyzed. This analysis was
done for a fixed number of 28 circuits per
carrier and a 30-second wafer + tooling
exchange time.
As shown in Table 2, a dual-table
system, on average, doubles the relative
throughput of a single cell per circuit
solution. Generally, the placement speed
doubles, and the time spent exchanging
wafers + tooling is cut in half, resulting in
this improvement. The single- and dual-
table single system per circuit solutions
exhibit a 60% to 90% improvement in
throughput in this example. Secondly, the
Figure 4: Single system vs. a multiple dedicated system line.
overall variation from 2 to 4 to 8 unique
multiple systems, impacting placement model was created to allow for a device types has much less impact than
accuracy. Finally, moving substrates comprehensive sensitivity analysis. As the number of circuits per carrier noted
between 8 dedicated systems in a line mentioned, the most critical factors are in Table 1. Finally, the relative quantity
increases placement, fiducial find, and the time it takes to automatically change of each unique die type has a more
potentially, temperature variability, wafers and change associated end effector significant impact than the number of
further degrading placement accuracy. tooling to support a new die type, the unique die types, mainly due to a greater
Based on typical system variability number of circuits to be assembled per impact on the total number of dies on the
data, it is estimated that all these carrier, and the number of unique die circuit (Figure 5).
factors will increase the defective types to be assembled per circuit.
placement ppm per device from a The sections below discuss the impacts Economic model summary
typical value of 100ppm to 400ppm for that a number of parameters have on HI An economic model was created to
a 4-die HI device. assembly economics. assess the economic impacts of yield,
The third challenge is that increased Impact of circuits per carrier and depreciation per circuit, OPEX, and
operator attention will be required per wafer and tooling change time. Table utilization. Pricing for a single-wafer
line with up to 8 machines in a line, 2 summarizes the relative throughput of table single system per circuit solution
as will increased floor space. This will assembled circuits for a single system per was arbitrarily set to $1mil. The price per
increase the overall operational expense circuit solution vs. a single die per system machine for the single dedicated system
(OPEX) cost for the line proportional to solution. The comparison is made for a per die type solution was set at $500k.
the number of systems in the line. single-system solution configured with A key observation from the economic
The fourth challenge is utilization. a single-wafer table and a single-system model is that, while depreciation cost per
Creating a dedicated lines per circuit solution configured with dual-wafer assembled circuit is the typical factor used
configuration versus a single cell that tables. The time to exchange unique for solution comparison, the assembly yield
can handle any circuit will reduce wafers and end effector tooling for unique has a much more significant impact on the
typical utilization. In addition, material die types was varied from 15 seconds overall manufacturing cost (Table 3).
scheduling and downtime typically to 60 seconds. For this example, it was For the single-bay single system per
reduce a single-system solution to 85% assumed the circuit had four unique die circuit solution, the depreciation cost is
utilization. With a 4-system solution, types, with the quantity of die per die only 30.7% of the total assembly cost.
these multi-system factors are expected to type of 8, 4, 2, and 1, respectively. Two other factors heavily influence
reduce utilization further to, at best, 60%. Table 2 shows that over the full range total assembly cost: total scrap per unit
of scenarios for circuits per carrier and produced and operator cost. Operator cost
Throughput sensitivity analysis wafer + tooling exchange time, a single is assumed to be directly proportional
To better understand the overall impact system per circuit solution delivers to the number of systems. Based on
of the parameters noted above on HI superior throughput. This advantage an estimated increase in defective
assembly economics, a mathematical ranges from 12% in the corner case of placements from 100ppm to 400ppm for

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