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trench decoupling capacitors on a silicon communication protocols have eluded us me well. I also wish to acknowledge
interposer. (We did not call it 2.5D, which so far. Perhaps, protocol translator dielets DARPA, SRC, SEMI, NSF, NIST, the
later became the abominable terminology offer a pathway. UCLA CHIPS Consortium members,
that should be banned, in my opinion.) There are many issues that I have not and the UC system, who have generously
This work was presented at the now- talked about here, but which are very sustained our work. This article is an
defunct 3D ASIP conference in 2013 along important. One issue is that many of abridged version of the short course I
with a product announcement. Since then, these advanced packages do not allow for gave at IEDM 2022.
the industry has focused on large processor rework, therefore, redundancy and self-
dies connected at ~40-50μm solder bump repair are going to be important. (We References
pitch to stacked memory dies via a silicon have proposed the use of utility dielets 1. S. S. Iye r, “ He t e r oge n e ou s
interposer. This is a good development to perform these and other functions.) i nteg rat ion for perfor mance
that has driven the artificial intelligence/ Another issue is thermal: as we bring the and scaling,” IEEE Trans. on
machine learning (AI/ML) applications. dies closer, there is no space to spread Components, Packaging and
Heterogeneous integration, however, is heat laterally so the heat needs to be Manufacturing Tech., vol. 6, no. 7,
a lot more than a memory and processor extracted vertically. Additionally, power pp. 973-982, July 2016.
chip tied together! Additionally, 500- delivery is a challenge. There is active 2. S. S. Iyer, S. Jangam, B. Vaisband,
2
836mm dies are not chiplets or dielets work going on in these areas and steady, “Silicon interconnect fabric: A
either! We need to have a commercially- incremental progress is being made for us versatile heterogeneous integration
viable roadmap that reduces “bump” to be optimistic. platform for AI systems,” in IBM
pitch, trace/wiring pitch, reduces dielet/ Jour. of Research and Development,
chiplet size and inter-dielet spacing, so Summary vol. 63, no. 6, pp. 5:1-5:16, 1 Nov.-
that dies can butt together on an extremely To summarize, fine-pitch heterogeneous Dec. 2019.
planar substrate. All these are difficult integration of a wide variety of small 3. S. Jangam, S. S. Iyer, “Silicon-
engineering problems, but well within dielets offers a path to reduced size, Interconnect fabric for fine-pitch
the capability of the microelectronics lower power, and potentially lower cost (≤10μm) heterogeneous integration,”
industry. Heterogeneous integration with at the functional system level. It’s no IEEE Trans. on Components,
diversely-sourced dielets presents unique longer about shrinking transistors, but Packaging and Manufacturing Tech.,
supply chain and trust challenges. For more about miniaturizing systems with vol. 11, no. 5, pp. 727-738, May 2021,
example, if you design a chip/chiplet, the a diversity of components—not just doi: 10.1109/TCPMT.2021.3075219.
foundry manufactures and delivers dies or transistors! The heterogeneous integration 4. S. S. Nagi, et al., “A 16nm 784-
dielets, and when singly-packaged, we call roadmap and its allied manufacturing core digital signal processor
it a chip. When many chips are packaged roadmap, the Manufacturing Roadmap for array, assembled as a 2 × 2 dielet
together, however, we call it a module. All Heterogeneous Integration and Packaging w it h 10μ m pitch i nterd ielet
this calls for an independent packaging (MRHIEP) provide valuable guidance I/O for runtime multi-program
and test facility that can deal with as we embark on the post-Moore’s Law reconfiguration,” IEEE Jour. of
multiple fabs, multiple nodes, multiple era. But the message is clear: feature Solid-State Circuits, vol. 58, no. 1,
material systems, and the like, and an scale down and system scale out. We pp. 111-123, Jan. 2023, doi: 10.1109/
immensely trustworthy relationship with will also need a more rigorous design JSSC.2022.3212685.
multiple fabs. methodology that borrows concepts, 5. ht t p: // w w w.b e t a si g ht s . n e t /
Today, there is no dielet marketplace such as process design kits (PDKs) from wordpress/?p=1216
(other than perhaps high-bandwidth silicon, and a predictable scaling roadmap 6. C . H o r n b u c k l e , S . S . Iye r,
memories [HBMs]—and try getting for packaging. “Passive silicon inter posers
those!). We need to have a dielet with deep trench decoupling for
discovery system based on aggregated Acknowledgments heterogeneous integration of
IP that are selected and fabricated using I would like to thank the many disparate technologies,” 3DASIP
a statistical usage model (e.g., which IPs colleagues in industry and academia presentation, Dec. 2013. The charts
occur together and how often they are who have been generous in teaching that were presented are available
used). This is going to require a lot of me about packaging (I am a relative from the author.
cooperation, transparency, and perhaps latecomer to this field), my students, who
some I/P standardization. Universal unbeknownst to them, have also taught

Biography
Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair
in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering
Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous
Integration and Performance Scaling (UCLA CHIPS). He is a fellow of IEEE, APS, iMAPS and NAI, as well
as a Distinguished Lecturer of IEEE EDS and EPS. He is a Distinguished Alumnus of IIT Bombay. He received
the IEEE Daniel Noble Medal for Emerging Technologies in 2012, and the 2020 iMAPS Daniel C. Hughes Jr.
Memorial award, and the iMAPS Distinguished Educator Award in 2021. Email s.s.iyer@ucla.edu

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26 Chip Scale Review March • April • 2023 [ChipScaleReview.com]