Page 24 - Chip Scale Review_March April_2023-digital

the skin effect only compound these at sub-10μm pitches. but more on cost. Now that calculus
difficulties. The dual realization that Why has it taken so long to address has changed and there is realization
silicon scaling had slowed down and the problems noted above? Primarily, that, especially in high-performance
packaging had left much performance silicon CMOS scaling was more or computing, advanced packaging can
on the table has led to a feverish less a sure thing, and one could get provide extraordinary value. This
amount of work on how to address the more perfor mance and transistor value comes pr i ma r ily f rom t he
packaging problem, and, as seen in density by scaling. Packaging, on increased bandwidth and reduced
Figure 1, there has been a significant the other hand, did not provide this latency of inter-chip communication
scaling of key packaging metrics. kind of value and very often was an at lower energy per bit transmitted.
For example, at UCLA CHIPS, we afterthought. The focus of classical This is accomplished in three ways:
routinely connect dies to the substrate packaging, therefore, was not on value, 1) Decreasing the pitch at which the
dies are connected to the substrate
(the so-called bump or pillar pitch); 2)
Reducing the wiring pitch (also called
trace pitch) on the substrate to sub-μm
dimensions; and 3) Reducing the die-
to-die separation on the substrate to
sub-50μm dimensions. A major reason
we have made such dramatic progress
is that we have borrowed immensely
from decades of silicon technology
including the use of silicon as the
substrate. It’s no surprise that silicon
fabs lead in this segment of packaging!
It turns out that silicon is an incredibly
versatile packaging material.
Si wafers are unbelievably flat and
thermally-matched to the silicon dies.
This allows for fine lithography (i.e.,
it’s very difficult to write on a warped
surface). The thermal conductivity of
silicon is about a third that of copper,
and unlike an organic PCB, offers a
viable heat extraction path (typically
only 10% of the power is extracted via
the organic PCB). This is important
as heat extraction is a serious issue
for high-performance systems. Two
a rg u me nt s t hat have be e n ma de
against using silicon are cost and the
brittleness of silicon wafers.
Silicon with a few layers of fine-
pitch wiring are indeed cost effective
compared to FR4 boards where even
sub-10μm pitch wiring is difficult
to achieve (silicon becomes ver y
ex p e n sive w h e n you bu i ld t i ny
FinFETS or nanosheet transistors
with 20 wir ing levels). The cost
can be reduced further by going to
P metallu rgical-g rade silicon used
RoHS
in the photovoltaics (PV) industry.
Handling techniques in silicon fabs
where breakage is almost non-existent
can also be used in packaging. The
elimination of solder in the assembly
process has allowed us to scale the
“ bu mp” pit ch. Solde r is ne e de d
in classical packaging to provide
compliance to the easily war ped

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