Page 27 - Chip Scale Review_March April_2023-digital

This means the probability of reuse is high, on a silicon interconnect fabric and To realize the full potential of the
while the opposite is true for large die. This simple communication protocols) were SuperCHIPS concept, however, we do
trend is shown in the grey line. Testing demonstrated and verified at UCLA need to increase the diversity of the chips
complexity – shown in the green line – CHIPS in 2022 for the first time in a used in these assemblies. Back in 2013,
decreases as die content reduces up to a functional assembly that employed a our group at IBM built (for Semtech)
point, but very small dies present testing scalable 1mm X 1mm DSP chiplet design what was very likely the first commercial
challenges. Finally, as dies become smaller, (dielets were manufactured by TSMC interposer [5] product that employed two
there is less space to accommodate pads and GlobalFoundries) as the building 90nm SiGe transceiver chips and a 45nm
(for testing or I/Os). This means the I/O block [4]. It’s only a matter of time before application-specific integrated circuit
sizes need to shrink, and by implication, the these concepts make it to the commercial (ASIC) with embedded dynamic random
“bump” pitch as well. Large dies can also market place. access memory (DRAM) and deep-
use small bump pitches, but smaller dies,
or dielets, cannot afford to do so because
there is not enough space available. Smaller
dielets generate less data and can do with
fewer I/Os. These arguments are explained
in much more detail in [2].
If you put the considerations noted above
together, you find there is a sweet spot – a
golden dielet regime – where the dielet size
2
is about 1-100mm and the connection pitch
to the substrate is between 2 and 10μm.
These dimensions are not a coincidence.
They can be derived from the size of
typical I/P blocks on an SoC and the pitch
of the wires connecting them—typically
the fat wire vias.
Reducing the “bump” pitch and the
inter-die spacings has another beneficial We Take Care of the
consequence. The wire inductance between
chips becomes negligible and the wire Fine Work
behaves not as a transmission line, as is the
case in PCBs, but as a simple capacitive
load similar to wires on the chip. This Wafer Level Packaging
means we do not need to worry about
terminations, reflections, inter-symbol
interference, and such. The I/O, therefore,
becomes very simple—just a bunch of
cascaded inverter-drivers. It also turns out
that we have a lot more wires available in
this scenario compared to a PCB. So, we
do not need to serialize the data and we can
send it in its native parallel format, at much
lower speeds (think DRAMS that activate REDISTRIBUTION LAYER COPPER PILLAR COMPONENT ASSEMBLY WAFER METALLIZATION
COMPONENT ASSEMBLY
an entire row, but we need to serialize this
data to send it off-chip and at very high
speeds). This reduces power significantly,
as shown in Figure 3b. We have proposed a
simple hard protocol called “SuperCHIPS”
(the catchy acronym Simple Universal
Parallel intERface for CHIPS) that allows
one to do this and a figure of merit that
allows us to compare different protocols ELECTROLESS PLATING SOLDER BUMPING WAFER THINNING WAFER DICING
beyond merely energy per bit, but also
allows for the accounting of I/O area, drive
strength, and bit error rate (Figure 5) [3].
Many of the concepts discussed
above (i.e., <10μm bump pitch, 2μm
t races, 50μm die-to-die spacing,
1mm X 1mm dielets all assembled pactech.com

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