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References                           11.  R. Weerasekera, S. Bhattacharys,   heterogeneous integration,” IEEE/
          1.  Y. Chiang, S. Tai, W. Wu, J. Yeh, C.   K. Chang, V. Rao, “Semiconductor   ECTC Proc., June 2021, pp. 96-
             Wang, D. Yu, “InFO-oS (integrated   Package and Method of Forming     100.
             fan-out on substrate) technology   the Same,” US 11,018,080, date of   15.  O. J. You, J. Li, D. Ho, J. Li, M.
             for advanced chiplet integration,”   patent: May 25, 2021.            Zhuang, D. Lai, et al., “Electrical
             Proc. of IEEE/ECTC, May 2021,   12.  TSMC’s A n nual Tech nolog y     performances of fan-out embedded
             pp. 130-135.                       Symposium, Aug. 25, 2020.          bridge,” IEEE/ECTC Proc., June
          2.  J. H. Lau, Semiconductor Advanced   13.  L. Cao, T. Lee, Y. Chang, S.   2021, pp. 2030-2034.
             Packaging, Springer, 2021.         Huang, J. On, E. Lin, O. Yang,   16.  C. Chong, T. Lim, D. Ho, H.
          3.  J. H. Lau,  Chiplet Design and    “Advanced HDFO packaging           Yong, C. Choong, S. Lim, et al.,
             He te r oge n e o u s In te g r a t i o n   solutions for chiplets integration   “Heterogeneous integration with
             Packaging, Springer, 2023.         in HPC application,” IEEE/ECTC     embedded fine  interconnect,”
          4.  J. H. Lau, “Recent advances and   Proc., June 2021, pp. 8-13.        IEEE/ ECTC Proc., June 2021, pp.
             trends in advanced packaging,”   14.  J. Lee, G. Yong, M. Jeong, J. Jeon,   2216- 2221.
             IEEE Trans. on CPMT, Vol. 12,      D. Han, M. Lee, et al., “S-connect
             No. 2, Feb. 2022, pp. 228-252.     fan-out interposer for next-gen
          5.  J. H. Lau, “Recent advances and
             trends in multiple system and
             heterogeneous integration with
             TSV-less interposers,” IEEE Trans.
             on CPMT, Vol. 12, No. 9, Sept.
             2022, pp. 1271-1281.
          6.  J. H. Lau, “Recent advances and
             trends in multiple system and
             heterogeneous integration with
             TSV-interposers,” IEEE Trans. on
             CPMT, Vol. 13, No. 1, Jan. 2023,
             pp. 3-25.
          7.  D. Sharma, G. Pasdast, Z. Qian,
             K. Aygun, “Universal chiplet
             interconnect express (UCIe®):
             an open industry standard for
             in novations with chiplets at
             package level,” IEEE Trans. on
             CPMT, Vol. 122, No. 9, Sept. 2022,
             pp. 1423-1431.
          8.  J. H. Lau, “Recent advances and
             trends in fan-out wafer/panel-level
             packaging,” ASME Trans., Jour.
             of Electronic Packaging, Vol. 141,
             Dec. 2019, pp. 1-27.
          9.  C. Hsiu ng, A. Su nd a r raja n,
             “Methods and Apparatus for
             Wafer-Level  Die  Bridge,”  US
             10,651,126, date of patent: May 12,
             2020.
          10.  J. H. Lau, C. Ko, P. Lin, T. Tseng,
             R. Tain, H. Yang, “Package
             Structure and Manufacturing
             Method Thereof,” US 11,410,933,
             date of patent: Aug. 9, 2022.

                       Biography
                         John H. Lau is a senior special project assistant at Unimicron Technology Corporation, Taoyuan City,
                       Taiwan (ROC). He has more than 40 years of R&D and manufacturing experience in semiconductor packaging,
                       518 peer-reviewed papers, 43 issued and pending US patents, and 23 textbooks. He is an ASME Fellow,
                       IEEE Fellow, and IMAPS Fellow. He earned a PhD degree from the U. of Illinois at Urbana-Champaign.
                       Email John_Lau@unimicron.com




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