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Figure 3: The FO-MCM solution.
redistribution layer (FORDL) became massive bandwidth and high power interconnection length comes from
an essential routing technology between efficiency. The HBM standard has the growing HBM package sizes. The
the die-to-die interconnection area. eight channels. Each channel is 128 package widths of HBM2 and HBM2E
Additionally, because of high demand interconnect pins, with a per pin data are 7.8mm and 10mm, respectively.
for processors to process and analyze big rate of 2Gbps. Higher data rates per pin Meanwhile, the package width of HBM3
data at high speed and in large volume, (3.2Gbps) are supported in the recent has been increased to 11mm and the
the size of RDLs has evolved to finer updates to the HBM2E standard, hence, interconnection length between the
lines/spaces. This evolution allows one the eight channels could provide an HBM and SoC PHY (physical layer) is
to route more metal traces and layers to aggregate bandwidth up to 409.6GBps. ~6mm (Figure 4). In order to understand
satisfy the design requirement. In the future, the speed of HBM3 will be which is the most suitable topology for
The HBM interface is used to connect increased to more than 6.4Gbps. routing HBM interfaces, a transient
CPU/GPU/application-specific integrated In this paper, the electrical design time domain simulation and the eye
circuits (ASICs) to large dynamic challenges using the polymer-based diagrams obtained from this simulation
random access memories (DRAMs), fan-out wafer-level package (FOWLP) were used to qualify the physical
especially for leading-edge high- RDL (see Figure 3) to implement structure. To qualify the suitability of
performance computing, graphics, and these interfaces are discussed and the different configurations and the
networking applications that demand presented. I ncreasi ng SoC-H BM HBM specifications that were used, it
Figure 4: The current status of FO-MCM packaging development.
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36 Chip Scale Review March • April • 2023 [ChipScaleReview.com]
