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since 2020 and has been in mass
production for switch applications at
SPIL. Additional requirements have
been imposed on assembly houses that
need to come up with turn-key solutions
for FO-MCM devices to be integrated
with heterogeneous chips such as
IPD or HBM. In addition, this paper
summarized the reliability test results
whereby all reliability conditions passed
the MSL4, TCT700, u-HAST96, and
HTSL1000 test conditions. The integrated
de-cap capacitors suppress the power
domain noise and enhance the HBM3
signal integrity at a high data rate. FO-
MCM is one type of chiplet package
platform that is designed for lower cost
and a high data rate transmission package
and meets the need for a high I/O count
and a large number of Cu wires densely
packed within a constrained package size.

References
Figure 6: Adding capacitors at positions 1, 2 and 3 can reduce power noise by 30%. 1. B. Sabi, “Advanced packaging in
processes. In the chip-last process – channels are affected by the impedance of the new world of data,” Elec. Comp.
also known as RDL first – the chips the power distribution network (PDN) and and Tech. Conference (ECTC) 2017.
are not integrated into the packaging the SSO pattern. In the FO-MCM package, 2. Y. L. Huang, ”Challenges of large
processes until the RDL on the carrier traditionally adding capacitors at positions fan-out multi-chip module and fine
wafer has been preformed. The chip- 1 and 2 can reduce power noise by about Cu line space,” ECTC 2020.
last process has less known-good die 15%. In the high-end integrated HBM2E 3. J. Li, “Large-size multi-layered
(KGD) yield concerns compared with package, a 2.5D package is usually fa n- out R DL pa ck ag i ng for
the chip-first process. In cycle time used with an embedded deep trench heterogeneous integration,” IEEE
comparison, the chip-last process also capacitor (DTC). The DTC embedded 23rd Elec. Packaging Tech. Conf.
has the advantage of a shorter process in the interposer can be very close to the (EPTC) 2021.
time, although the electric capacity is chip side and therefore, will have greatly 4. L. C. T. Lee, “Advanced HDFO
almost the same (see Figure 5). improved electrical noise. Nevertheless, packaging solutions for chiplets
adding the capacitor configuration in integration in HPC Application,”
Power noise position 3 can be comparable to the effect IEEE 71st ECTC, 2021.
For next-generation HBM, the power of a DTC, and can reduce the power 5. S-L. Liu, “Assembly technology
noise margin is a critical parameter to supply noise by about 15%. Positions 1, 2, for FO-MCM with HBM in HPC
assess the system performance—and the and 3 are connected to a traditional MLCC application,” IMAPS 2022.
power noise margin is decreased from capacitor, or silicon capacitors, to reduce 6. F. Kao, “Next generation fan out
previous generations because of the higher power noise by 30% (see Figure 6). assembly technology in chiplet
data rate and the lower operating voltage. packaging to improve power loss and
The power supply voltage fluctuation Summary rout-ability,” SPIL, IMPACT 2021.
degrades the signal output waveform FO -MCM tech nolog y has been 7. M . L i a o , “ H e t e r o g e n e ou s
performance. The output voltage at parallel demonstrated to have the maturity for integration fan-out package solution
simultaneous switching output (SSO) homogeneous silicon chip integration for HPC/AI application,” SPIL,
IMPACT 2022.

Biographies
Teny Shih is a Department Manager, Corporate R&D at Siliconware Precision Industries Co., Ltd., Taichung,
Taiwan, R.O.C. He has over 25 years of industrial experience focusing on development of advanced packaging
technology and analysis and measurement of electrical characteristics. He has published more than four
conference papers and has 6 patents. Email: tenyshih@spil.com.tw

Sam Lin is a Manager, Corporate R&D at Siliconware Precision Industries Co., Ltd., Taichung, Taiwan, R.O.C.
He has 12 years of industrial experience focusing on package electrical analysis, measurement and product
application analysis. In recent years, he has focused on 2.5D, 3DIC, FO-MCM and FO-EB advanced packaging research.

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