Page 36 - ChipScale_Jan-Feb_2020-digital

Common issues for fan-out
FOWLP has piqued the interest of the semiconductor
industry because of its high-performance level and flexibility
for multi-die configuration. However, die shift and warpage
have remained the top challenges of high-volume production
both with respect to yield and cycle time. Multiple research
studies from both equipment makers and material suppliers
have been conducted to resolve these issues.
Die shift. The die location plays an important role for both
package design and manufacturing. The dies have predefined
location and pitch for specific package sizes. This information is
needed during the making of the photomask for the lithography
process. Die shift is a defect in which the die placement has
an offset from the predefined location by a certain distance.
This offset, if high enough, will cause a lithography or
patterning issue in which the bond pads do not align with the
mask, thereby causing open/close electrical interconnects.
Warpage. Warpage is one of the defects that is inherent to
the structure. Because the wafer/panel becomes a heterogenous
material on account of the combination of silicon and molding
compound, the materials’ properties will act on each other.
In this case, the CTE mismatch creates an imbalance in the
expansion and contraction of the material when processed
through thermal treatment. This affects both 1) productivity,
which creates issues regarding handling and automation,
and 2) yield, where it potentially causes high thickness
variation during the coating process, or pattern defect
during exposure.
Understanding warpage and its impact. Research has
been done by John Lau, et al. [1], regarding the top six process
stages that are hugely affected by wafer/panel warpage. For
the chip-first structure, once the wafer is debonded from
the carrier, warpage immediately becomes apparent. In
the face-down version commonly referred to as embedded
wafer-level ball grid array (eWLB), the process that suffers
warpage post-debond is the photo process. This process,
aside from handling issues, will encounter yield problems
when warpage is not minimized. In the face-up version, the
process affected post-debond is the top-grinding process.
The surface grinding process is performed to expose the
connection embedded in the molding compound, and with
warpage (to a certain degree), the wafer/panel becomes
unprocessable. It is critical that warpage is at its minimum
post-debond.
The ease of handling warp wafers/panels is affected by two
factors: 1) the warpage degree, which can be calculated as:

warpage = RPDmax – RPDmin;
and 2) warpage profile, which is the surface topography of
the wafer.
The war page prof iles in the reconstit uted wafer
change depending on several factors, such as the
silicon-to-mold density, the die shape (i.e., square
and rectangular), and the number of RDLs, and for
the panel level, the array arrangement as well (see
Figure 2). To ensure that the profile does not significantly
affect the handling system, it is crucial to reduce the
warpage to <1mm after debonding so that the RDL or top
grinding process can take place.

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