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opens, and other errors, the schedule is (or even designer) to the next, making it • If two shapes in the package design
already blown. HDAP designers must virtually impossible for EDA companies to database have the same text labels
have something they can do during support all possible spreadsheets. while they are physically disconnected,
early verification to fix obvious HDAP But if using these different spreadsheet this is reported as an “open;” and
LVS issues, even before the full LVS formats isn’t practical, there’s still a package • If two shapes in the package design
verification can be completed. To enable design database, isn’t there? Is there no database have different text labels while
and support this kind of early verification way to do simple opens/shorts checking they are physically connected, this is
in a timely manner, they need an just with this data? Actually, there could reported as a “short.”
automated methodology for HDAP LVS be. EDA tools can implement a simple
checking that can be run without all the automated approach that still provides A lt hou g h t h i s c e r t a i n l y i s n’t
final components. useful information to designers: comprehensive LVS verification (as there is

Design dependence
In SoC LVS verification, the LVS
rules deck is only dependent on the
SoC technology node information (i.e.,
GDSII layers). HDAP LVS adds another
complexity: die placements. While an HDAP
LVS rule deck is obviously dependent on the
GDSII layers of the interposer, die1, die2,
etc., it is also dependent on where the dies
(and interposer for 2.5D) are placed in the
HDAP design itself. However, it would be an
exhaustive, and nearly impossible, process
for the foundry/OSATS to build HDAP LVS
rule decks that account for all possible die
and interposer placement combinations.
Even if such rules were possible for a “two
dies on an interposer” design, it quickly
becomes impractical as the number of dies
and substrates increase in HDAPs.
So, with the acknowledgment that
HDAP verification flows on the design side
are far from mature, the EDA companies
have to ask: What level of HDAP LVS
verification can be achieved with different
levels of package knowledge and expertise,
and different types of available data? The
answer might surprise you. Let’s explore
what HDAP LVS verification might look
like in different flows for different cases.

HDAP LVS options
The following sections discuss various
HDAP LVS verification flow options.
Package/interposer connectivity
checking without a schematic/design
intent. The concept of a “source netlist”
in a standard format is still relatively
new to package designers. Traditionally,
they use manual spreadsheets to plan the RoHS
connectivity from die to package to external P
I/O on a PCB design. Although it’s difficult
to apply this methodology to HDAP
verification, some HDAP designers still use
spreadsheets, whether it’s because the pin
count number is so low that it is practical, or
they’re simply resistant to change. However,
the format and organization of those
spreadsheets varies from one company

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