Page 34 - ChipScale_Jan-Feb_2020-digital

As such, the size tolerance equals the to the substrate. Further investigations will pulse pitch. In addition, wet etching used
positional tolerance values. show whether and to what extent better in LIDE is typically a batch process and
The lowest roughness value obtained cavity depth tolerance can be achieved. does not contribute significantly to the
by LIDE is approximately Ra ≈ 0.5µm. Cost contributions. To evaluate overall process costs.
Although the bottom surface of the a new manufacturing process, it is
pockets created by LIDE does not meet essential to consider its cost and, in Summary
optical standard requirements, most particular, to understand its influencing Glass capping wafers with steep side
capping applications do not require such a factors. Even though LIDE is a very fast walls have been achieved with the help
low roughness. manufacturing process, it remains a direct of laser-induced deep etching (LIDE)
Cavity depth shows a standard deviation writing technology. The pulse pitch is technology. The size tolerances of the
of 3.9µm and is therefore significantly larger the main contributor to the overall cost. cavities, their depth value (>300µm), as
than the other tolerances. The reason for Fortunately, there is a tradeoff between an well as their position tolerance, have been
this is suspected to be insufficient control of acceptable bottom surface roughness and measured. They are within specifications
the mechanically-guided laser head relative a manufacturing cost to choose an optimal to accommodate WLP packaging. The
bottom pocket surface roughness is Ra ≈
0.5µm, well within what is necessary to
accommodate the dies.
In conclusion, we believe that LIDE
technology is a good candidate to
manufacture closed cavities for WLP,
taking into account the fact that the
steep side walls achieved allow higher
population densities of the die packing.

References
1. R. Ostholt, “Novel method for high-
volume via formation in solid–core
glass for IC substrates,” Chip Scale
Review, Sep/Oct 2017, Vol. 21/5.
2. R. Tummala, “Future of Embedding
and Fan-Out Technologies,” Chip Scale
Review, Vol. 21 (2017) 20-28.
3. R. Ostholt, “Laser-induced deep etching
of glass (LIDE) and its contribution to
heterogeneous integration,” Semi 3D
Summit 2019, Dresden, Germany.
4. J. Thomason, “Glass fibre strength—
a review with relation to composite
recycling,” (2016); https://www.mdpi.
com/journal/fibers
5. Z. Zhang, C.P. Wong, “Design,
Process and Reliability of Wafer Level
Packaging,” from the book Micro-
E-Tec Interconnect AG, Mr. Pablo Rodriguez, Lengnau Switzerland and Opto- Electronics Materials
Phone : +41 32 654 15 50, E-mail: p.rodriguez@e-tec.com and Structures: Physics, Mechanics,
Design, Reliability, Packaging, (pp.
B135 – B150), Jan 2007.

Biographies
Roman Ostholt is Managing Director Electronics at LPKF Laser & Electronics AG, Garbsen, Germany.
He earned a Dipl.-Ing. in Mechanical Engineering and a Dr.-Ing. at RWTH Aachen U. At LPKF Laser
& Electronics AG he is responsible for the development of LIDE technology, for which he received
an award at Productronica 2017. He is an inventor and co-inventor of multiple patents in that field.
Email Roman.Ostholt@lpkf.com or info@vitrion.com
Norbert Ambrosius is Team Leader Process Engineering at LPKF Laser & Electronics AG, Garbsen,
Germany. He received a Dipl.-Ing. in Mechanical Engineering at RWTH Aachen U. and started his career
as a project manager in the Technology Development department at LPKF Laser & Electronics AG, where he developed
the LIDE process. In his current role, he is responsible for the process and technology development of LIDE technology.
He is an inventor and co-inventor of multiple patents in that field.

32
32 Chip Scale Review January • February • 2020 [ChipScaleReview.com]