January February 2025
Volume 29, Number 1
There have been any number of market drivers for advanced semiconductor packaging over the years, including improved form factor, power, and operational temperature requirements to accommodate the demand for ever-smaller consumer electronics. Automotive applications have also been a significant driver for packaging. More recently, the semiconductor industry is embracing the process improvements needed to implement artificial intelligence in a broad swath of military and commercial applications. The cover article discusses an integrated wet processing platform that meets the needs of chips for AI applications, and that also has a low cost of ownership.
Cover image courtesy of iStock/Pony Wang
March April 2025
Volume 29, Number 2
Advanced packaging substrates, such as glass-based interposers combined with automated packaging processes, can overcome manufacturing bottlenecks in photonic component assembly. This approach will enable photonic and electronic co- packaged subsystems to scale to large-volume production. As a result, mass market demands--including data center communications, artificial intelligence, sensing and diagnostics—will be addressed. The cover image shows the packaging of a microlens array to a flip-chip assembled InP photonic integrated circuit on a glass electrical
interposer with BGA contacts.
Cover photo courtesy of Tyndall National Institute
May June 2025
Volume 29, Number 3
The growing size of AI clusters is pushing data centers to their physical limits, necessitating the development of multi-site AI clusters to distribute workloads. These clusters rely on coherent ZR optics for high-speed data transfer, which is why it is imperative to increase the yield of such cutting-edge optical modules. This increase in yield can be enabled by using efficient PIC testing.
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Cover image courtesy of iStock/Quantico69
July August 2024
Volume 28, Number 4
To continue scaling while increasing transistor density, the industry is turning to methods such as using the backside of the chip for wiring in addition to traditional front-side back-end-of-line wiring. The use of backside power delivery networks (BS-PDNs) can be done using several different schemes. However, as use of the wafer backside evolves, backside/frontside overlay tolerance is expected to grow tighter, resulting in challenges for patterning as discussed in the cover article.
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Cover image courtesy of iStock/Kynny
