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designs, which gives an important role and opportunity for design and intellectual property (IP) houses. In reusing IP blocks, time can
be saved on product development time. If we consider the integration of a memory cube and a processing unit, between 5 to 7 companies
are involved on average, which adds to cost and complexity. That’s why the supply chain is considered from the beginning of product
development. Figure 1 shows the suppliers
involved in 3D packaging technologies.
Four different types of players want to claim a
share of the growing $5.5 billion stacking market.
“Foundries, integrated device manufacturers
(IDMs), OSATS and intellectual property (IP)
companies all want their share of the stacking
business. Foundries, like TSMC, UMC, and
GLOBALFOUNDRIES, dominate the TSV
heterogeneous stacking technology market
because of their ability to produce the interposer
in-house. Intel is the only IDM that is trying
to compete in this sector with its “Foveros”
technology. In the 3D stacked-memory market,
the battle is between the big 3 IDMs: Samsung,
SK Hynix, and Micron. These companies will
continue to reign supreme in the stacked-memory
market. 3D SoC is a foundry technology.
Most probably one foundry will manufacture
the technology to ensure high yield and limit
risks. TSMC is leading the time-to-market
race ahead of GLOBALFOUNDRIES. For the
TSV-less technologies, the game is a bit more
intense between foundries, IDMs, OSATS and
substrate makers. Samsung, Intel and TSMC
are into both with- and without-TSV technology
development. OSATS like ASE have introduced
their FOCoS technology to the market in 2016.
Other players like Amkor developed their
proprietary technology but are still waiting for
orders. The substrate companies, like Shinko,
Unimicron, and lately, Fujitsu Interconnect, are
still in R&D. Xperi will have a positive impact
on the market as its hybrid bonding technology is
midway between technologies with- and without-
TSV. The other advantage of Xperi is that its
technology is compatible with both high and
mid/low-end segments. Foundries, IDMs, and IP
companies have the advantage over OSATS in
stacking technology, where the latter encounter
difficulties in getting orders.

References
1. F. Shoo, “Stacking technologies: the road
ahead,” Chip Scale Review, Nov/Dec 2019,
pp.: 4-8.
2. “2.5D/3D TSV & Wafer Level Integration
Technology & Market updates report,” Yole
Développement, 2020.

Biography
Santosh Kumar is a Principal Analyst and Director Packaging, Assembly & Substrates, Yole Développement,
Korea. He is involved in the market, technology and strategic analyses of the microelectronic assembly and
packaging technologies. He is the author of several reports on fan-out/fan-in WLP, flip-chip, and 3D/2.5D
packaging and received Bachelor’s and Master’s degrees in Engineering from the Indian Institute of Technology
(IIT), Roorkee and U. of Seoul, respectively. Email Santosh.kumar@yole.fr

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