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approximately 50% higher bandwidth and 100% additional capacity Proven

boasts a 3.2Gbps data transfer speed per pin, which is 33% faster
than the previous-generation HBM2. Flashbolt has a density of
16Gb/die, double the capacity of the previous generation. With these
improvements, a single Samsung HBM2E package will offer a 410
gigabytes-per- second (GBps) data bandwidth and 16GB of memory.
In August 2019, SK Hynix announced an HBM2E DRAM product
with the industry’s highest bandwidth. The new HBM2E boasts an

compared to the previous HBM2. It supports an over 460 Gigabyte
(GB)-per-second bandwidth based on the 3.6Gbps speed performance Used in 5 Billion SiP Packages
per pin with 1,024 data I/Os. By using through-silicon via (TSV) in the past 5 years
technology, a maximum of eight 16 gigabit chips are vertically
stacked, forming a single, dense package of 16GB data capacity.
Compared with traditional wire bond connections, DRAM chips that
are stacked using TSV interconnects result in a shorter signal path
and a high-speed performance with lower power consumption. While
traditional structures package memory chips into a module form that
can be connected to system boards, an HBM chip is packaged closely
to logic chips, such as GPUs, leading to shorter distances between
chips, which further accelerates data processing rates.

3D packaging for AI
Various 2.5D/3D packaging solutions, with or without TSV, are
available today for packaging AI chips for inference and training.
As shown in [1, Figure 1], TSV-based technologies include 2.5D
Si interposer (e.g., chip-on-wafer-on-substrate [CoWoS]), 3D TSV
stacking (e.g., for HBM stack), Foveros, 3D SoC, etc. TSV-less
packaging technologies include embedded multi-die interconnect
bridge (EMIB), integrated fan-out package on package (InFO-PoP),
integrated fan-out on substrate (InFO-oS), fan-out chip-on-substrate
®
(FOCoS), silicon wafer integrated fan-out SWIFT , integrated thin-
®
film high-density organic package (i-THOP ), RDL interposer, etc.
The positioning of various 3D packaging technologies in terms of I/O
and package size is shown in [1, Figure 4].
3D/2.5D TSV and heterogeneous integration technologies have
emerged as the choice technology for AI, and particularly for deep
learning applications, as they provide higher bandwidth, low latency,
and low power consumption. For AI accelerators, it is important to
keep logic and high-capacity memory as close as possible to provide
low latency and lower power. When two chips or more are integrated From water-soluble to no-clean processes,
on an interposer, the distance between logic and memory is shortened, Indium Corporation’s wide portfolio of
which enables lower latency and lower power consumption. DRAM,
based on a 3D TSV solution, offers an unequaled bandwidth solders are PROVEN to solve various
performance because of the ability of the TSV solution to connect industry challenges.
several layers of the device.
3D IC and 2.5D solutions based on interposer are not stand-alone
products—they need to be integrated onto a final package to be Learn more:
functional. The interposer acts as an intermediate layer between the www.indium.com/SiP/CSR
dies; it is the solution that has enabled die partitioning. Si interposers
provide a high-density routing connection between logic and memory. askus@indium.com
Interposers can be made out of silicon, glass and organic laminate
materials. Only silicon is used in commercial applications, but glass
and laminate are under development. However, silicon interposers
are the only solution ≤1µm for routing today. Silicon interposer is
considered costly, so many alternative technologies from outsourced
semiconductor assembly and test suppliers (OSATS) and integrated
device manufacturers (IDMs) are in development, and some are
already in production, e.g., EMIB from Intel, InFOoS from TSMC,
FOCoS from ASE, etc. Some of the recent developments in the 3D
stacking technologies are listed in the sections below.

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