Page 38 - Chip Scale Review_January-February_2024-digital

Figure 4: An interface part in xSI.
together (for example: short VDD_
SENSE and AVDD on the interposer
to VDD on the package) while these
power nets are disconnected in the
system source netlist. Users often
include this information in a list (e.g.,
text file, CSV). Without including
this list in the xSI/Calibre 3DSTACK
flow for system-level LVS, many LVS
errors are reported. In this case, it
is difficult for users to distinguish
between the intended errors and the
real errors. To resolve this challenge,
the shorts list should be considered
while generating the source netlist
for Calibre 3DSTACK so that the nets
present in the shorts list are merged.
Calibre 3DSTACK allows a net
mapping feature, as presented in the
previous section. This feature can
be utilized to account for the shorts
list. The shorts list can be considered
as a net map f ile, a nd it ca n be
automatically included in the Calibre
runset using a wizard that is integrated
with xSI, as shown in Figure 5.

Assembly verification challenges
Let’s consider a typical silicon
interposer case in which one foundry
is manufacturing both the interposer
and the dies included in the 2.5D-

36 Chip Scale Review January • February • 2024 [ChipScaleReview.com]
36