Page 37 - Chip Scale Review_January-February_2024-digital

System connectivity exceptions in The interface part function is used to Although the net names are different,
3D-IC multi-substrate assemblies connect two different substrates in the “TEST_CLK” signal is correctly
In some cases, a system source xSI (called “floorplans” or designs). tracked across the system due to
n e t l i s t i s no t e no u g h f o r LV S An example of an interface part is the existence of the “C4P” part (the
ve r i f i c a t io n of 3D - IC m u l t i pl e highlighted (on the left) in Figure 4. interface part).
substrate systems. In these cases, As seen in Figure 4, there are two Another thing to consider is tool
designers need to “short” some signals substrates: “Interposer” and “Package.” support for known shorts. In multi-
together in the substrate layout. These For the “TEST_CLK” signal, there are substrate 3D-IC assemblies it is a
shorts create a mismatch between the two different net names: “TEST_CLK” common practice for designers to short
layout and the source netlist. Although in the interposer domain and “pkg_ some unneeded signals to the ground
these differences are repor ted in TEST_CLK” in the package domain. plane or short different power planes
the LVS comparison results, they
are intended by the user (usually
temporarily).
For the user to differentiate between
the intended LVS issues versus the
real LVS issues, the intended LVS
issues need to be somehow waived
from the LVS results. One obvious
solution is to modif y the system
source netlist to match the physical
layout implementation. However, this
is not desirable because the system
source netlist is required to be golden
and frozen across different physical
i mplement at ion s a nd ite r at ion s.
Therefore, designers need a quick,
automated, and flexible way to handle
connectivity exceptions in a 3D-IC
design that enables them to waive
intended shorts in the LVS comparison
re s u lt s . O u r Ca l i b re 3DSTACK
supports a “net mapping” feature
that can be utilized to account for the
intended shorts. The shorts list can
be considered a net map file, and it
can be automatically included in the
runset using a wizard that is integrated
with xSI.
A n o t h e r c h a l l e ng e c a n a r i s e
when an assembly includes both an
interposer and a package substrate for
the same connection; the IC design
team (building the silicon interposer)
may u se a d if fe re nt net na m i ng
methodology than the packaging team
(building the organic substrate). The
system-level designer then ends up in
a situation where the same port name
can be assigned to two different net
names. For example, the same die-to-
ball grid array (BGA) connection can
be assigned to two different net names:
C4_PKG (packaging team naming) and
C4_INT (interposer team naming).
Our xSI can recognize a connection
across substrates, even when two
different net names are assigned to
the connection. This is achieved by
applying the xSI interface part feature.

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