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And in the case of extremely large exposure field (e.g., 250mm
x 250mm) lithography systems, these differences in overlay
create a major yield challenge, especially for high-volume
manufacturing.
First, let’s define total overlay. Total overlay is the summation
of the overlay errors for all RDL layers, with respect to the
bookending final layers on either side of the panel (Figure 1).
Cumulative overlay drift from individual RDL buildup layers
can significantly increase overall trace length. This may result
in higher interconnect resistance, parasitic effects and poor
performance for high-speed and high-frequency applications.
As each RDL is added to the film stack, layer-to-layer overlay
data needs to be continuously monitored. If the total overlay
error exceeds specifications at any point, and at any location
on the panel, corrective action must be taken to mitigate total
overlay drift or else the design resistance specifications for a
package may be exceeded.
You can think about total overlay like this: if the overlay
drifts 5µm per layer, and there are 10 layers, the total RDL
length will increase by 45µm. This problem is exacerbated as
the number of layers increases, i.e., in a 24-layer RDL stack, the
interconnect length would increase by 115µm.
To address the total overlay challenge, manufacturers should
employ an overlay tracking system, one that incorporates
metrology, lithography and analytics that records measurements
for every RDL-to-via overlay across the entire panel and sums
the vectors, from layer to layer, as the process stack grows. With
such a system, the manufacturing team could use inspection and
data analytics to track and compensate for multi-layer overlay
drift. The tracking system would generate an error signal when
cumulative overlay error exceeds thresholds, and the required
overlay correction offsets would then be calculated and sent to
the lithography system. Without a suitable tracking system in
place, manufacturers have no way of knowing if RDL resistance
meets specification until final electrical test (e-test). By that
point, resources, time and money will have been wasted.

Yield challenges
Now that we’ve discussed total overlay drift, let’s explore
AICS package yield and its importance in fostering a cost-
effective, high-throughput process. As previously mentioned,
AICS have relatively few packages per panel. For example,
a 510mm x 515mm AICS panel can only accommodate 16
packages (120mm x 120mm) compared to FOPLP, which could
have over 2,300 packages. That’s a significant difference. One
defective package on an AICS could result in a 6.25% yield
loss, whereas with FOPLP, one defective package may only
represent a 0.04% yield loss.
To make matters even more complicated, the yield challenge
is exacerbated because as the AICS package size increases to
150mm x 150mm, a single defective package failure results in
an 11% yield loss, which is a significant decrease in an industry
that operates under extremely narrow margins. In addition,
the requirement to process both the frontside and backside of
the AICS offers another risk: surface contamination leading to
defects that result in yield loss.
It takes a few weeks to complete the processing of an AICS.
Only by knowing the yield of an entire fab’s AICS inventory,
in real time, will productivity be evaluated accurately.
Furthermore, panel yield needs to be assessed in terms of

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