Page 12 - Chip Scale Review_November-December_2023-digital
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Figure 6: SAM images of defective bonding (delamination and voiding) caused by surface particles.





















        Figure 7: Automatic optical inspection (AOI) of the a) surface and b) sidewall of singulated dies of a tape-frame wafer after thinning and the saw-dicing process. A
        large number of particles (black) can be seen adhering to the sidewall. c-d) An incorrect further cleaning detaches and redeposits the particles onto the die surface. c-e)
        The organic nature of the particles revealed by energy-dispersive X-ray spectroscopy inspection suggests tape adhesive as the origin. If not properly removed, f) these
        particles can cause die delamination after bonding, as seen under SAM inspection.
        normal quantile plot in Figure 8c, which   yield impact of queue time between the   variance increases with a more complex
        shows a >99.5% continuity electrical test   various process steps, as batch-mode   bonding configuration, where >3-5 different
        yield (a significant improvement from   processing makes it difficult to control   chiplets are in the roadmap to be bonded to
        pre-optimization data). The process   queue time. Samples were processed with   the same substrate. Three bonded wafers
        improvement was reflected in overall mean   a 36-hour queue time and compared with   from the “delayed” lot were compared to
        resistance and variability.        the baseline; in the high-volume production   the baseline in Figure 9. Adding queue
          The same test vehicle was further used to   case, one could expect a queue time of 1   time leads to significantly lower yield (80%)
        characterize the process-induced possible   to 2 days, and not just time, but also its   vs. the reference case (98%).




















        Figure 8: Post optimization: a) CSAM result showing void-free bonding, b) a wafer contour plot of 10,000-connectivity daisy-chains resistance, and c) Normal-quantile
        plot of 10,000 connectivity DC showing >99.5% yield (~230-dies)—a significant improvement from pre-process optimization.

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