Page 49 - Chip Scale Review_May June_2022-digital
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a flip-chip device. One option to improve   technology [5]. This embedded chip   using laser-based photolithography. A
        topside cooling of a FIWLP device is to   technology mounted chips face up in   similar technique has been implemented by
        form a thermal pad under each array solder   cavities using liquid-dispensed chip   Deca on its FOPLP processing line. It uses
        pad. This could be done by opening vias   attach adhesive. The combination of chip   an automated imaging system to measure
        in the first dielectric layer directly under   placement tolerances and excessive chip   each chip’s exact location based upon
        each array pad to the chip passivation layer.   movement resulted in die location errors   its corner I/O pads. It then recomputes
        During the first RDL metal processing   of 25 to 100µm. This technique measured   the laser drill data base and RDL laser
        step, the thermal vias could be metallized,   the exact position of each chip corner pad   patterning data and forms the microvias in
        forming thermally-conductive posts that   using an automated vision system and   the correct locations and correctly routes
        provide each solder bump with a direct   adjusted microvia locations and RDL   the RDL lines and pads [6]. This technique
        thermal path to the chip.          routing. This is only applicable to FIWLP   would be needed to extend molded-wafer
          Higher device switching frequencies.
        Higher device switching frequencies can
        create additional RDL line cross talk
        that can affect switching margins. Faster
        switching may require isolating ground
        planes within the RDL layers to either
        provide a controlled impedance transmission
        line, or to minimize cross talk between
        adjacent lines. Lower supply voltages
        generate higher power and ground currents   LEADERS IN
        that will increase resistive line losses and
        a higher device sensitivity to power rail   MICRO DISPENSING
        droop and surges, thereby lowering device
        operating margins.                         TECHNOLOGY
          Chip misplacement and movement.
        A unique problem for all molded-wafer      SMALL REPEATABLE VOLUMES
        FIWLP devices, are lateral and rotational   ARE A CHALLENGE, BUT NOT
        chip placement tolerances and chip         IMPOSSIBLE IF YOU HAVE BEEN
        movement after placement. Whereas chip     CREATING THEM AS LONG AS WE HAVE.
        locations for on-wafer FIWLP processes
        are precise down to fractions of microns, all
        molded carrier processes use pick and place
        machines that inherently have placement    TO DO IT WELL,
        tolerances more than an order of magnitude
        higher, i.e., multiple microns. Depending   WE PROVIDE THREE THINGS:
        on the processes and the organic materials
        used to bond the chip to the carrier before
        molding, there can be chip movement after
        placement included during adhesive curing,   Dispensing Expertise in a variety of microelectronic
        molding and molding material curing. The   packaging applications.
        molded carrier shrinks during the molding
        process, thereby adding a varying global   Feasibility Testing & Process Verification based
        offset. Finally, the molded-wafer has a    on years of product engineering, material flow testing
        higher composite CTE than a wafer does     and software control.
        resulting in a varying chip position caused
        by temperature changes from the elevated   Product Development for patented valves,
        temperature during adhesive and molding    dispensing cartridges, needles, and accessories.
        material curing and the lower temperature
        during photolithography steps. These chip
        position tolerances will limit the ability of
        molded-wafer FIWLP processes to shrink
        RDL line widths and solder bump pitches.
          RDL adaption. One approach to            Our Micro Dispensing product line is proven and trusted by
        overcoming chip misplacement and chip      manufacturers in semiconductor, electronics assembly, medical
        movement issues is adapting the locations   device and electro-mechanical assembly the world over.
        of microvias and RDL routing for each      www.dltechnology.com.
        device based on its precise position. This
        was first done using the GE high-density
        interconnect (HDI) multi-chip interconnect   216 River Street, Haverhill, MA 01832  •  P: 978.374.6451  •  F: 978.372.4889  •  info@dltechnology.com


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