Page 44 - Chip Scale Review_May June_2022-digital

Acknowledgments Trans. on CPMT, 2018, Vol. 8, Issue 9, Kuah, K. Wu, et al., “Warpage and
The author would like to thank his Sept. 2018, pp. 1561-1572. thermal characterization of fan-out
co-authors of the papers [1-4,6,7,9-13] 3. J. H. Lau, C. Ko, C. Lin, T. Tseng, K. wafer-level packaging,” IEEE Trans.
cited in this brief article. Their useful Yang, T. Xia, et al., “Fan-out panel- on CPMT, Vol. 7, Issue 10, Oct. 2017,
and constructive contributions are level packaging of Mini-LED RGB pp. 1729-1738.
greatly appreciated. display,” IEEE Trans. on CPMT, Vol. 7. J. H. Lau, M. Li, Y. Li, M. Li, I. Au, T.
11, No. 5, May 2021, pp. 739-747. Chen, et al., “Warpage measurements
References 4. J. H. Lau, M. Li, Q. Li, I. Xu, T. and characterizations of FOWLP
1. J. H. Lau, M. Li, M. Li, T. Chen, I. Chen, Z. Li, et al., “Design, materials, with large chips and multiple RDLs,”
Xu, X. Qing, et al., “Fan-out wafer- process, and fabrication of fan-out IEEE Trans. on CPMT, Vol. 8, Issue
level packaging for heterogeneous wafer-level packaging,” IEEE Trans. 10, Oct. 2018, pp. 1729-1737.
integration,” IEEE Trans. on on CPMT. Vol. 8, Issue 6, June 2018, 8. N. Motohashi, T. Kimura, K. Mineo,
CPMT, Vol. 8, Issue 9, Sept. 2018, pp. 991-1002. Y. Yamada, T. Nishiyama, K.
pp. 1544-1560. 5. C. Tseng, C. Liu, C. Wu, D. Yu, Shibuya, “System in a wafer-level
2. C. Ko, H. Yang, J. H. Lau, M. Li, “InFO (wafer-level integrated fan-out) package technology with RDL-first
M. Li, C. Lin, et al., “Chip-first technology,” IEEE/ECTC Proc., May process,” IEEE/ECTC Proc., May
fan-out panel-level packaging for 2016, pp. 1- 6. 2011, pp. 59–64.
heterogeneous integration,” IEEE 6. J. H. Lau, M. Li, D. Tian, N. Fan, E. 9. J. H. Lau, C. Ko, K. Yang, C. Peng,
T. Xia, P. Lin, et al., “Panel-level
fan-out RDL-first packaging for
heterogeneous integration,” IEEE
Trans. on CPMT, Vol. 10, No. 7, July
2020, pp. 1125-1137.
10. J. H. Lau, C. Ko, T. Peng, K, Yang, T.
Xia, P. Lin, et al., “Chip-last (RDL-first)
fan-out panel-level packaging (FOPLP)
for heterogeneous integration,” IMAPS
Trans., Jour. of Microelectronics and
Electronic Packaging, Vol. 17, No. 3,
Oct. 2020, pp. 89-98.
11. J. H. Lau, G. Chen, J. Huang, C.
Yang, N. Liu, T. Tseng, “Hybrid
substrate by fan-out RDL-first panel-
level packaging, IEEE Trans. on
CPMT, Vol. 11, No. 8, Aug. 2021, pp.
1301-1309.
12. C. Peng, J. H. Lau, C. Ko, P. Lee, E.
Lin, K. Yang, et al., “High-density
hybrid substrate for heterogeneous
integration,” IEEE Trans. on CPMT,
Vol. 12, No. 3, Mar. 2022, pp. 469-478.
13. J. H. Lau, “Recent advanced and
trends in advanced packaging,” IEEE
Trans. on CPMT, Vol. 12, No. 2, Feb.
2022, pp. 228-252.
14. C. Wang, T. Tang, C. Lin, C. Hsu,
J. Hsieh, C. Tsai, et al., “InFO_AiP
technology for high-performance and
compact 5G millimeter wave system
integration,” Proc. of IEEE/ECTC,
May 2018, pp. 202-207.

Biography
John H. Lau is a senior special project assistant at Unimicron Technology Corporation, Taoyuan City, Taiwan
(ROC). He has more than 40 years of R&D and manufacturing experience in semiconductor packaging,
510 peer-reviewed papers, 40 issued and pending US patents, and 22 textbooks. He is an ASME Fellow,
IEEE Fellow, and IMAPS Fellow. He earned a PhD degree from the U. of Illinois at Urbana-Champaign.
Email John_Lau@unimicron.com

42
42 Chip Scale Review May • June • 2022 [ChipScaleReview.com]