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FIWLP devices to the higher densities needed
to meet the next-generation microelectronic
devices. FIWLP devices fabricated on-wafer do
not need microvias and RDL adaption as there
is no chip placement step and no possibility of
chip movement.
Summary
The long running advances in semiconductor
processing capabilities are continuing with
higher I/O counts forecast for the foreseeable
future. One might assume that many of these
higher I/O count devices would require
FIWLP processing, but the fact is that high
I/O count chips, such as in high-performance
microprocessors and graphic processors that
go into personal computers, mainframes and
servers, as well as application and graphic
processors that go into mobile devices, will be
designed as flip-chip devices. They do not need
additional package-level processing, such as
FIWLP processing, as they will be area-array
devices. FIWLP will continue to target chips
designed for wire bonding with I/O counts
in the low (~10 to ~50) to medium (~50 to a
couple 100) range. FIWLP technologies still
need to go to finer lines and tighter pad pitches
as low and medium I/O count chips go through
die shrinks that will require finer line RDL and
tighter pitch solder bumps.

References
1. R. Fillion, “Advanced microelectronics
packaging technologies and their
performances,” Chip Scale Review, Nov/
Dec 2021 pp.10-17.
2. G. Ridly, “Introduction to flip chip: what,
where, why, how,” Flipchips.com, Oct.
2000.
3. R. Fillion, “Embedded chip build-up using
fine-line interconnect,” ECTC 2007.
4. “Advanced packaging quarterly market
monitor,” Yole Développement, March
2020.
5. “High-density copper/polyimide overlay
interconnections,” R. O. Carlson, et al.,
IEPC 1988.
6. “New commercialization of Deca’s fan-out
technology,” i-micronews.com, March 2022.

Biography
Ray Fillion is Managing Director at Fillion Consulting, Schenectady, NY. He retired after 40 years from the
GE Global Research Center where he worked in various engineering, management, business development and
licensing positions in embedded chip, MCMs, 3D modules and power electronics. He has over 100 publications,
has 45 issued U.S. patents and was the lead inventor on the GE Embedded Chip Build-Up and the GE Power
Overlay technologies. Email fillion.consulting@gmail.com

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