Page 27 - Chip Scale Review_March April_2022-digital
P. 27
References
1. B. Sabi, “Advanced packaging in the
new world of data,” Elec. Comp. and
Tech. Conference (ECTC) 2017.
2. Po-Yao Chuang, “Hybrid fan-out
package for vertical heterogeneous
integration,” IEEE 70th ECTC 2020.
3. Q. Ding, “High-bandwidth low-
power 2.5D interconnect modeling
and design,” IEEE 70th ECTC 2020.
4. R. M a h a j a n, “S c a l i n g f o r
heterogeneous integration,” Georgia
Tech Packaging Research Center
Industry-Academic Consortium
2020.
5. R. Manepalli, “Advanced packaging
technologies for heterogeneous
i nt eg r at ion: chal le nge s a nd
oppor t u n ities,” 31st A n nual
Electronic Packaging Symposium
and Semicon West 2019.
6. L. Cao Teck Lee, “Advanced HDFO
packaging solutions for chiplets
integration in HPC application,”
IEEE 71st ECTC 2021.
7. Y. P. Chiang, “InFO_oS (Integrated
Fan-Out on Substrate) technology
for advanced chiplet integration,”
IEEE 71st ECTC 2021.
8. JiHun Lee, “S-Connect Fan-
out I nt e r pose r for next-ge n
heterogeneous integration,” IEEE
71st ECTC 2021.
9. JaeYoon Kim, “Chip-last HDFO
(high-density fan-out) interposer-
PoP,” IEEE 71st ECTC 2021.
10. G. Pan, “Warpage assessment
of chip module in chip-last FO-
MCM platform for non-wetting
risk evaluation,” IEEE 15th Inter.
Microsystems, Packaging, Assembly
and Circuits Tech. (IMPACT) 2020.
11. J. Li, “Large-size multi-layered
fa n- out R DL pa ck ag i ng for
heterogeneous integration,” IEEE
23th Elec. Packaging Tech. Conf.
(EPTC) 2021.
Biographies
Nicholas Kao is a Department Manager, Corporate R&D at Siliconware Precision Industries Co., Ltd., Taichung,
Taiwan, R.O.C. He received his MS degree from the Institute of Applied Mechanics of National Taiwan U. in 1999 and
has 22 years of industry experience focusing on package stress analysis, stress measurement and product application
analysis. He has published over 20 conference papers and patents. Email nicholas@SPIL.com.tw
Jay Li is a Deputy Manager, Corporate R&D at Siliconware Precision Industries Co., Ltd., Taichung, Taiwan,
R.O.C. He received his MS degree from National Central U., Taiwan and MBA degree from San Diego State U.,
U.S.A. He is focusing on 2.5D, 3DIC, FO-MCM, and FO-EB advanced packaging research. He has over four years working in
the semiconductor industry and has published four papers.
25
Chip Scale Review March • April • 2022 [ChipScaleReview.com] 25