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Large-field, fine-resolution lithography enables

next-generation panel-level packaging

By John Chang [Onto Innovation]
R apidly growing demand for

new types of functionality
a c r o s s a n e x p a n d i n g
range of applications, including 5G
communication, smartphones, data
centers, servers, high-performance
computing (HPC), artificial intelligence
(AI) and the Internet of Things (IoT),
is driving a fundamental shift in the
way electronic devices are designed and Figure 1: Heterogeneous integration enables next-generation device performance gains by combining multiple
manufactured. Gone are the days when silicon nodes and designs inside one package. The package size is expected to grow significantly. SOURCE: Cadence
advances were defined by an increasing
number of shrinking transistors with
ever-faster switching times and lower
power consumption, all fabricated as a
single, monolithic integrated circuit (IC).
Many of today’s most advanced systems
integrate multiple die, each optimized
for a specific capability and fabricated
with a process designed specifically
for that type of circuit. These disparate
chips are then connected using advanced
packaging (AP) technologies, a process
known as heterogeneous integration (HI)
(Figure 1).
One example of HI uses advanced
IC substrates (AICS) in a process
known as ultra-high density (UHD)
panel fan-out. This fan-out panel-level Figure 2: The number of 80mm x 80mm packages that fit on a 300mm wafer compared with the number of
process (FOPLP) is a redistribution 80mm x 80mm packages that fit on a 515mm x 510mm panel.
lines (RDL)-first approach, where
many layers of patterned conductive T he lit hog r aphy challenge for We describe here the use of our large-
and insulating material are processed large heterogeneous integration is field lithography system (JetStep®
on both sides of a large panel to route the limited size of the exposure field X500) to expose 250mm x 250mm
electrical signals between the integrated (typically 60mm x 60mm or less) for substrates in a single shot on 515mm x
chips, which are added last. Once the most currently available lithography 510mm panels. Our evaluation included:
RDL layers are complete, solder bumps systems. Smaller-field systems can 1) critical dimension (CD) control for
are added to form connection points be used to pattern large substrates by 3µm, 5µm and 6µm lines/spaces, and
that will mate with matching connection stitching together multiple exposures, 15μm and 20μm vias; 2) CD uniformity
pads on the component ICs. Package but this affects both productivity and across the exposure field; and 3) overlay
substrate sizes are expected to reach yield because of the need for multiple accuracy. We used copper clad laminate
150mm x 150mm in the next few years. exposures of multiple reticles and the (CCL) and Anjinomoto build-up film
Panels, which may be 500mm x 500mm risk of errors at the stitching boundaries. (ABF) panels for resolution, and glass
or larger, can accommodate many more A large exposure field would eliminate panels with liquid resist for overlay and
packages per panel than the substrates these impediments. However, there are uniformity. The large field eliminates
used in wafer-level processes, which also challenges associated with a large stitching, allows the exposure of more
are restricted to round, wafer-like exposure field. These include panel large package substrates in a single shot
substrates of 300mm or less in diameter warpage and distortion, which can and requires fewer shots to complete a
(Figure 2). impact critical dimensions, uniformity panel. Figure 3 compares the exposure
and overlay. layout for a large field (250mm x 250mm)

42 Chip Scale Review November • December • 2021 [ChipScaleReview.com]
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