Page 54 - ChipScale_Mar-Apr_2021-digital
P. 54
etc.) in order to better understand the References silicon-on-insulator substrate,”
bonding process. Further research 1. A . P o l y a k o v , M . B a r t e k , Optical Materials Exp., vol. 3, no.
needs to be done on the reliability J . N . B u r g h a r t z , “A r e a - 1, pp. 35-46, 2013; doi: 10.1364/
of the bond. It is concluded that the s ele c t ive a d h e sive b o n d i ng OME.3.000035.
proposed process technology is a u s i n g p ho t o s e n s i t i v e B C B 3. D. Liang, G. Roelkens, R. Baets,
possible solution for bonding silicon for W LCSP applications,” J. J. E. Bowers, “Hybrid integrated
chips on a wafer substrate using a thin Elect ron. Packag., vol. 127, platforms for silicon photonics,”
and photostructurable adhesive layer. no. 1, p. 5 pages, 2005; doi: Mater ials, vol. 3, no. 3, pp.
10.1115/1.1846059. 1782-1802, 2010; doi: 10.3390/
Acknowledgment 2. S. Keyvaninia, M. Muneeb, S. ma3031782.
This article was previously published in Stanković, P. J. Van Veldhoven, 4. L. Yu, F. E. Tay, G. Xu, B. Chen,
the International Wafer-level Packaging D. Van Thourhout, G. Roelkens, M. Avram, C. Iliescu, “Adhesive
Conference 2020 Proceedings. It has been “Ultra-thin DVS-BCB adhesive bonding with SU-8 at wafer level
edited and reformatted for publication in bonding of III-V wafers, dies for microfluidic devices,” J. of
Chip Scale Review. and multiple dies to a patterned Physics Conf. Series, vol. 34,
no. 1, pp. 776-781, 2006; doi:
10.1088/1742-6596/34/1/128.
5. S . G . S e r r a , A . S c h n e i d e r,
K . M a l e c k i , S . E . Hu q , W.
Bren ner, “A si mple bondi ng
process of SU-8 to gla ss to
seal a microf luidic device,”
3 t h I n t . C o n f . o n M u l t i -
Material Micro Manufacture,
Borovets, Bulgaria, 2007; doi:
10.13140/2.1.2832.2082.
6. J. K i m, I. K i m, K.-W. Pai k,
“Investigation of various photo-
patternable adhesive materials
and their processing conditions,”
IEEE 61st Elec. Comp. and Tech.
Conf. (ECTC), Lake Buena Vista,
FL, USA, 2011; doi: 10.1109/
ECTC.2011.5898765.
7. M. Wiemer, C. Jia, M. Toepper, K.
Hauck, “Wafer bonding with BCB
and SU-8 for MEMS packaging,”
Elec. System Integration Tech.
Conf., Dresden, Germany, 2006;
doi: 10.1109/ESTC.2006.280194.
8. F. N i k l a u s , P. E n o k s s o n ,
P. G r i s s , E . K ä l v e s t e n , G .
St e m me, “ L ow- t e mp e r at u r e
wafer-level transfer bonding,”
J. of Microelectromechanical
Sys.; vol. 10, no. 4, 2001; doi:
10.1109/84.967375.
Biographies
Kai Hollstein is a PhD student at the Institute for Microelectronic Systems, RESRI Workgroup Hannover,
Leibniz U. Hannover, Germany. His research focuses on package development, thermal and thermomechanical
simulation of electronic packages and reliability analysis. Email kai.hollstein@ims.uni-hannover.de
Kirsten Weide-Zaage is extraordinary Professor at the Institute for Microelectronic Systems, and leader of
the RESRI Workgroup Hannover, Leibniz U. Hannover, Germany. Her main research activities are in the field
of microelectronic reliability with a focus on static and dynamical thermal-electrical-mechanical effects in
interconnects, packages, and on boards, as well as on the effects of corrosion and radiation on customer owned tooling (COT)
and TCAD simulations.
52
52 Chip Scale Review March • April • 2021 [ChipScaleReview.com]