Page 49 - ChipScale_Mar-Apr_2021-digital
P. 49

reliability for large-die flip-chip
            lead-free BGA package in power
            cycling and thermal cycling tests,”
            61st ECTC 2011, pp. 921-926.
          6. L. Garner, C. Zhang, K. S. Beh,
            K. Helms, Y. L. Tan, “Effect of
            compression loads on the solder
            joint reliability of flip-chip BGA
            packages,” 54th ECTC 2004, pp.
            692-698.
          7.  T- C.  C h iu ,  D.  E d wa rd s ,  M.
            Ahmad, “Ball grid array solder
            joint reliability under system-level
            compressive load,” IEEE Trans. on
            Device and Materials Reliability,
            vol. 10, no. 3, Sep. 2010, pp. 324-
            337.
          8. P. K. Bhatti, M. Pei, X. Fan,
            “Reliability analysis of SnPb and
            SnAgCu solder joints in FC-BGA
            packages with thermal enabling
            preload,” 56th ECTC 2006, pp.
            601-606.
          9.  X. Fan, M. Pei, P.K. Bhat ti,
            “Effect of finite element modeling
            techniques on solder joint fatigue
            life prediction of flip-chip BGA
            packages,” 56th ECTC 2006, pp.
            972-980.
         10. G. Gust afsson, I. Guven, V.
            Kradinov, E. Madenci, “Finite
            e l e m e n t  m o d e l i n g  o f  B G A
            packages for life prediction,” 50th
            ECTC 2000, pp. 1059-1063.
         11. L. F. Coffin, “A study of the
            effects of cyclic thermal stresses
            on ductile metal,” ASME Trans.,
            Vol. 76, pp. 931-950, 1954.
         12. JEDEC STANDARD Temperature                                                            RoHS
            Cycling JESD22-A104E.                                                                 P
         13. I PC - 9 7 01 A ,  “ P e r f o r m a nc e
            test methods and qualification
            requirements for surface mount
            solder attachments,” IPC, 2006.






                       Biographies
                         Manish Nayini is Senior Engineer, Packaging Engineering at Marvell Semiconductor, USA, Hopewell
                       Junction, NY. He works on thermomechanical simulations at the package- and board-level. He has been with
                       Marvell for the past year; prior to that, he worked for 3 years at Globalfoundries in the Advanced Packaging
                       Development Group. He has a Masters in Mechanical Engineering from Arizona State U., and a Bachelors in
                       Mechanical Engineering from BITS Pilani, Goa, India. Email mnayini@marvell.com

                          Timothy Horn is a Packaging Reliability Engineer at GLOBALFOUNDRIES, USA. After completing his
          BS in Microelectronic Engineering at RIT in 2015, he pursued a passion for material characterization through his work as a
          reliability engineer at GLOBALFOUNDRIES, USA and by working on his MS in Materials Science at UVM (expected in May,
          2021) as a part time endeavor.


                                                                                                             47
                                                             Chip Scale Review   March  •  April  •  2021   [ChipScaleReview.com]  47
   44   45   46   47   48   49   50   51   52   53   54