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350+ TECHNICAL PAPERS HIGHLIGHTS
COVERING: n 46 technical sessions with a
Fan-Out WLP & CSP total number of 350+ technical
3D & TSV Processing papers including:
• 10 topical sessions hosted
Heterogeneous Integration by the IP Subcommittee
Fine Pitch Flip-Chip n 5+ special invited sessions
MEMS & Sensors n 50+ live Q&A sessions
Advanced Substrates n 14 CEU-approved Professional
Development Courses
Advanced Wire Bonding n Multiple opportunities for
Flexible & Wearable Devices networking
RF Components n Technology Corner Exhibits,
Automotive Electronics showcasing industry-leading
product and service companies
Harsh Environment from around the world
Bio/Medical Devices n Various sponsorship
Thermal/Mech Simulation opportunities for your
company’s visibility
Interconnect Reliability n Great and professional digital
Optical Interconnects platform solution

imaging for die-first fan-out packaging die-last process. With this method, all of need for C4 and µbumps, which in turn
of heterogeneous devices utilizing high- the dies are fixed to a temporary carrier supports the use of smaller contact vias and
density organic interconnects for future with epoxy mold compound (EMC). After reduced line pitches. With the increased
high-performance computing (HPC) releasing the temporary carrier, the RDL area available after reducing the vias and
devices. In Figure 3a, two popular layer is built up, utilizing the compensated lines, additional I/Os can also be added.
packaging technologies for HPC that exposure and auto-wiring abilities of the These changes are possible with the direct
utilize a silicon interposer or embedded direct imaging system to connect the dies imaging system’s auto-wiring and high-
multi-die interconnect bridge (EMIB) and compensate for random die placement resolution capabilities. The proposed
techniques are shown. These processes offsets. The silicon interposer or embedded process enables advances in future high-
are referred to as “die-last processes” as silicon bridge interposers are no longer performance packaging that are expandable
the fan-out RDL patterns and interconnect needed, leading to an overall reduction in and enable higher I/O densities while
lines are built on the substrate before the process cost. In addition, package size is remaining cost effective. We believe these
dies are mounted. To connect the substrate not limited when using maskless exposure, benefits of the maskless exposure system
and dies, C4 bumps and µbumps are used. allowing for additional dies per package will expand packaging design beyond
Figure 3b shows our die-first proposal when larger substrates are selected. This current limitations, enabling the next
that eliminates the bumps required in the type of die-first process also removes the generation of dynamic device innovation.

Biographies
Shota Majima is a Process Engineer for semiconductor equipment working at SCREEN Semiconductor
Solutions, Kyoto, Japan. He engaged in the development of dry etching process for FEOL for 3 years as his first
career. After that, he joined lithography process development for the direct imaging tool and has engaged in the
development of various kinds of packaging technologies for 3 years. He holds a Master’s degree in Electronic
Engineering from Nara Institute of Science and Technology (NAIST). Email majima@screen.co.jp
David Hyde is a Product Engineer at SCREEN-SPE USA, Sunnyvale, CA. His early career focused on
prototyping solutions for power generation control systems before transitioning to semiconductors. He now
supports tool customization for existing product lines in addition to engaging in new product design and evaluation.

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