Page 52 - Chip Scale Review_January-February_2024-digital

selectively growing the III/V material in
pre-patterned trenches in Si. These high-
aspect-ratio trenches are very effective
in trapping the defects in the narrow
bottom part and allowing the growth of
high-quality, low-defectivity material
out of the trench. Overgrowing the nano-
ridge widens it towards the top, forming
a solid base for a device stack. The first
insights obtained from a GaAs/InGaP
case study will guide the optimization
of the target InGaAs/InP NRE HBT
devices (Figures 5-6).
Beyond direct growth, InP can
also be placed on Si using a wafer
reconstruction technology (Figure
4c). In this case, high-quality InP
substrates—with or without the active
layers—are diced into tiles during wafer Figure 6: Zoom-in of the 300mm Si wafer showing the dies with the InP NRE HBT structures.
constitution. The tiles are subsequently
attached to a Si wafer using a die-to- Towards heterogeneous integration Advanced laminate substrate technology
wafer bonding technique. The key Ultimately, the III/V-on-Si power is the most common way to integrate
challenges lie in the efficient transfer of amplifiers must be combined with CMOS- different RF components in a system-
the materials and the removal of the InP based components that take care of, e.g., in-package, and optimizations to make
substrate, for which several techniques calibration and control. Imec is looking it adaptable to higher frequencies are
are being considered. into various heterogeneous integration ongoing. Additionally, imec is exploring
options and weighing their pros and cons more advanced heterogeneous integration
for various use cases. options, including 2.5D interposer and 3D
integration technologies.
Especially for frequencies above
100GHz, it is important to note that the
antenna module starts to define the area
available for the transceiver. Indeed,
when going to higher frequencies, the
wavelength decreases, and the area of
the antenna array scales accordingly.
Above 100GHz, the antenna size becomes
smaller than the front-end module size,
which hardly scales in size with increasing
frequency. An interesting option for
large antenna array configurations is to
move the RF front-end module under
the antenna array. And this is where
3D integration technologies (either die-
to-wafer or wafer-to-wafer) come into
play, enabling short and well-defined
connections between the front-end module
and the antenna modules. However,
thermal management remains a great
concern for 3D integration, and being
able to provide effective heatsinks will be
crucial. Today, at imec, we are performing
a comprehensive system-technology-co-
optimization (STCO) analysis to evaluate
different technologies for 3D integration
and to guide the technology choices from
a system-level perspective.
For handheld devices, where a reduced
number of antennas can relax the
constraints, 2.5D interposer technology is
considered an interesting approach. This

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