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2
heterogeneous integration option uses Acknowledgment cm Fully Vertical GaN-on-Si Power
a layer stack with lithography-defined This paper was originally published Diodes by Selective Removal of Si
connections and even through-Si vias to in Compound Semiconductor (Vol. 29/ Substrates and Buffer Layers,” IEEE
communicate between III/V- and CMOS- Issue 5/pp. 46-51). It has been edited for Electron Device Letters, vol. 39,
based components. In this case, the III/ republication in Chip Scale Review. Issue 5, pp. 715-718.
V devices sit next to the CMOS chip, 8. K . H a r r o u ch e , e t a l .,“ H ig h
enabling better thermal management References performance and highly robust
because both chips can be in direct contact 1. N. C ol l a e r t , e t a l ., “ I I I -V/ AlN/GaN HEMTs for millimeter-
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Biography
Nadine Collaert is a Fellow and a Program Director at imec, Leuven, Belgium. She’s currently responsible for the
advanced RF program looking at the heterogeneous integration of III-V/III-N devices with advanced CMOS to tackle
the challenges of next-generation mobile communication. Previously, she was a Program Director of the logic beyond
Si program and has also been involved in the theory, design, and technology of FinFET devices, emerging memories,
and more. She has a PhD in Electrical Engineering from the KU Leuven, (co-) authored more than 400 publications,
and holds more than ten patents in device design and process technology. Email Nadine.Collaert@imec.be
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