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their verification signoffs before providing production data to
us for manufacturing and assembly processes.
This ability for accurate implementation of design rules,
manufacturing and assembly constraints into the EDA
and computer-aided manufacturing (CAM) design tools,
with the SmartPackage PADK enables users to quickly
highlight design restrictions early in the design process
limiting the number of product design cycles. To experience
these benefits, some investment in software and hardware
infrastructure may be necessary. Depending on the current
design environment, a high-powered Linux server will
need to be employed. This system will be tasked with
running the extensive manufacturing and assembly design
rule constraints on the manufacturing data that is destined
for fabrication.
We pioneered the development of PADKs in 2016. Users
receive support for PADKs to integrate them as a robust
component of their device development approach. The OSAT
can provide guidance for package design layout direction,
provide specific application training, and provide ongoing
design review support, using the latest software to incorporate
their packaging knowledge and experience into SmartPackage
PADK elements.
Which elements of a package assembly design kit exert
the most significant influence on design readiness? The
emphasis typically revolves around three key areas. The first
is the EDA start-point database, the second is design rules
constraint (DRC) sign-off verification, and the third is the
ability to validate the production data with the connections
list requirements.
A feature of SmartPackage PADK is the capability to
fine-tune the specific customized design-rule requirements
necessary for the device or design layout needs. The benefit
of device-specific design rule decks versus a fixed-node rule
deck system is that there is no need to provide careful and
extensive waivers to receive a passing verification report.

Test
We have been providing test services for heterogeneously-
integrated products since the inception of the 2.5D TSV
development cycle. The systemic approach of designing and
evaluating the test vehicles allows test engineers to develop
tests for critical aspects of the design before the live product.
There are a handful of test challenges that are common to all
heterogeneous chiplet packages. Chiplet interconnect integrity
is an important one.
Signal and power delivery to every chiplet within the
package requires careful layout, design and test during the
manufacturing process (Figure 7). Package material types
used, and the package constructs described earlier in this
article, impact the interconnect performance between the
chiplets and the pins exposed at the package level. This
includes both static connection quality with continuity,
leakage and transient ac timing, impedance matching and
signal crosstalk. Thermal performance of each of the chiplets
also impacts production testing. Thermal gradients due to non-
uniform chiplet temperatures are unavoidable. In a carefully
designed overall product architecture, design for test (DFT)
has access to all functional aspects of the product, which is an
important consideration.

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