Page 27 - Chip Scale Review_January-February_2024-digital

Readying the supply chain for chiplets and

heterogeneous IC packaging

By Mike Kelly, Dave Hiner, Ruben Fuentes, Jonathan Micksch, Vineet Pancholi [Amkor Technology, Inc.]
P roducts using heterogeneous system-on-chip (SoC) flip-chip ball grid DRAM memory (HBM), including

integration (HI) and chiplets
are here, they are in production, array (FCBGA) packages, but with several HBM2, HBM2e and HBM3. 2.5D TSV
was one of the first modern heterogeneous
key customizations.
and the current trend is for more products Currently, the packaging methodologies integrations using a high-density module
and more customers to develop and qualify employed in both production and to permit integration of the processor and
their products at outsourced semiconductor development encompass the following: 1) DRAM in the package itself. The silicon-
assembly and test suppliers (OSATs) and 2.5D through-silicon via (TSV) modules based interposer uses a Cu backend
foundry providers. relying on silicon interposers, i.e., 2.5D foundry fabrication process, and this
Combinations of processors and TSV; 2) modules utilizing high-density enables 1-2µm lines and spaces inside
memories have been around for years, fan-out (HDFO) multi-layer redistribution the IC package. This has been critical to
culminating at the high end with processors layer (RDL) approaches; or 3) modules enable a very wide parallel data base for
and high-bandwidth memory (HBM) to featuring bridges. These two-dimensional HBM communication. In many ways, it
address a fast-growing market for artificial constructions can be used for discrete die was this process development to enable
intelligence (AI) algorithm training. combinations as well as combinations of 2.5D TSV taking place in 2015-2018
Now, the functional de-partitioning of discrete die and 3D die stacks. The sections that set the stage for a new class of high-
die functions into chiplets is enabling a below discuss this developing landscape, density module-based products. These
broader and more potent impact on future starting first with the 2.5D TSV. new approaches targeted the next wave
designs. Chiplet approaches allow product of heterogeneous integrations as chiplets
performance increases to continue at a cost 2.5D TSV silicon interposers that were being designed and qualified in
point that is still compelling. Total silicon 2.5D TSV has been in high-volume just the last few years. In addition to the
costs can be lower due to better yields for manufacturing (HVM) at Amkor since latest processing know-how developed
smaller chiplets, and the opportunity to use 2017. The process flow begins with a full to support the TSV reveal process, a new
a mixture of silicon process nodes to further “TSV-reveal” capability, starting with class of ultra small Cu pillar bumps was
optimize the cost of the silicon. Integrated full thickness interposer wafers from required to support bump pitches in the
circuit (IC) packaging for heterogeneous one of the foundries, thinning to reveal 40-55µm range. This requires advanced
and chiplet approaches is more expensive, the Cu TSVs, followed with an inorganic plating tools and chemistries.
but this rise in package cost is offset by passivation step, under bump metallization Many of the foundational technologies
reduced total silicon expenses and favorable (UBM) and interposer backside bumping. noted above were used as is or extended
time-to-market advantages. This product space is dominated by to intersect other high-density modules
Moving to chiplets and HI implementations high-performance processors working such as HDFO and bridge-based product
has required a new infrastructure to be in combination with high-bandwidth developments (Figure 1).
established for IC and package design, IC
and package fabrication, and electrical test.
Design tools need to comprehend multiple
ICs in 2D and 3D physical configuration,
functional device electric test (E-Test)
and higher power densities. IC packaging
to support chiplets, and heterogeneous
constructions, have been a primary focus
for OSATs and foundries in recent years.
Multi-die products must be integrated
into one functional unit. Such integration
is accomplished using higher-density
integration approaches, namely wafer-scale
(chip-on-wafer, CoW) high-density modules
and high-density multi-chip modules
(MCMs), or both. High-density modules are
then attached to the IC package substrate in
a production environment like the venerable Figure 1: High-density module-based products.

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