Page 24 - Chip Scale Review_January-February_2024-digital

Acknowledgments 4. R. Radojcic, “More-than-Moore edited by John H. Lau, Springer
Additional co-authors of this article 2.5D and 3D SiP integration,” ISBN 978-981-10-8883-4 ISBN
are: Brian Tyrell, Kenneth Schultz, and DOI 10.1007/978-3-319-52548-8_2. 978-981-10-8884-1 (eBook) https://
Paul W. Juodawlkis, all from MIT Lincoln 5. R. N. Das, V. Calmidi, M. D. Poliks, doi.org/10.1007/978-981-10-8884-1.
Laboratory. The authors also gratefully V. R. Markovich, “Nanofluids, 13. Advances in Embedded and Fan-
acknowledge Lenny Johnson, Karen nanogels and nanopastes for Out Wafer-Level Packaging
Harmon, Peter Murphy, Chris Thoummaraj, electronic packaging,” 2010 Proc. Technologies, edited by Beth
John Liddell, Chris O’Connell, Terry Weir, 60th ECTC, Las Vegas, NV, USA, Keser and Steffen Kroehnert,
Mike Miszka, Chad Stark, and Marcus 2010, pp. 1231-1238, doi: 10.1109/ WILEY 2019, https://lccn.loc.
Sherwin for useful discussions and valuable ECTC.2010.5490857. gov/2018034374.
technical assistance. This research was 6. R. N. Das, et al., “Fabrication 14. P. Coudrain, et al., “Active
funded by the Assistant Secretary of and electrical characterization of interposer technology for chiplet-
Defense for Research & Engineering under embedded actives and passives ba sed a dva nced 3D system
Air Force Contract No. FA8721-05-C-0002. for system-level analysis: Towards architectures,” 2019 IEEE 69th
The views and conclusions contained herein size, weight and power (SWaP) ECTC, Las Vegas, NV, USA,
are those of the authors and should not be reduction,” 2012 IEEE 62nd 2019, pp. 569-578, doi: 10.1109/
interpreted as necessarily representing ECTC, San Diego, CA, USA, ECTC.2019.00092.
the official policies or endorsements, 2012, pp. 1593-1598, doi: 10.1109/ 15. K. K. Ryu, K. A. McIntosh, S.
either expressed or implied, of the U.S. ECTC.2012.6249049. Rabe, J. Ciampi, R. D. Lambert,
government. This paper was originally 7. R. N. Das, F. D. Egitto, J. M. R. Das, et al., “Rapid prototyping
presented at the 2023 IEEE 73rd Electronic Lauffer, E. Chenelly, M. D. Polliks, of si ng le - phot o n - s e n sit ive
Components and Technology Conference “Versatile Z-axis interconnection- backside-illuminated silicon
(ECTC). based core -less tech nolog y avalanche photodiode arrays,”
solutions for next-generation Proc. SPIE 10980, Image Sensing
References packaging,” 2013 IEEE 63rd Technologies: Materials, Devices,
1. R. N. Das, F. D. Egitto, J. Lauffer, ECTC, Las Vegas, NV, USA, Systems, and Applications VI,
B. Bonitz, B. Wilson, F. Marconi, 2013, pp. 1728-1733, doi: 10.1109/ 109800L (13 May 2019); https://doi.
et al., “3D-interconnect approach ECTC.2013.6575808. org/10.1117/12.2520798.
for high-end electronics,” IEEE 8. F. D . E g i t t o , R . N . D a s , 16. K. K. Ryu, B. F. Aull, M. Collins,
Elec. Comp. & Tech. Conf. Proc. G . E . T ho m a s , S . B a g e n , N. Pestana, J. Ciampi, R. Das,
(ECTC), 2012, 1333-1339. “Miniaturization of electronic et al., “Geiger-mode avalanche
2. R. N. Das, F. D. Egitto, S. G. substrates for medical device photodiode arrays fabricated on
Rosser, E. Kopp, B. Bonitz, R. applications,” 45th IMAPS, 186- SOI engineered-substrates,” Proc.
Rai, “3D integration of system- 191(2012). SPIE 12089, Advanced Photon
in-package (SiP) using organic 9. Tom Coughlin, “Chiplets For All,” Cou nt i ng Tech n iques X V I,
interposer: Toward SiP-interposer- Forbes, May 11, 2019. 120890C (30 May 2022); https://
SiP for high-end electronics,” 46th 10. C. Tseng, “InFO (wafer-level doi.org/10.1117/12.2618610.
Inter. Symp. on Microelectronics integrated fan-out) technology,” 17. B. Tyrrell, K. Anderson, J. Baker,
(IMAPS), 531-537(2013). 66th ECTC, May 2016, pp. 1–6. R. Berger, M. Brown, C. Colonero,
3. L. Engla nd , E. Tremble, I. 11. A. Cardoso, L. Dias, E. Fernandes, et al., “Time delay integration and
Arsovski, W. Sauter, “Advanced et al., “Development of novel in-pixel spatiotemporal filtering
packaging drivers/opportunities high-density system integration using a nanoscale digital CMOS
to support emerging artificial solutions in FOWLP-complex and focal plane readout,” IEEE Trans.
intelligence applications,” 2019 thin wafer-level SiP and wafer-level on Electron Devices, vol. 56,
Elect ron Devices Tech. and 3D packages,” 67th ECTC, May no. 11, Nov. 2009, pp. 2516-23.
Manufacturing Conf. (EDTM), pp. 2017, pp. 14–21.
209-11. 12. Fan-out Wafer-level-Packaging,

Biography
Rabindra N. Das is a Member of the Technical Staff in the Advanced Technology Division of MIT Lincoln
Laboratory, Lexington, MA. Prior to MIT, he was a Principal Engineer at Endicott Interconnect Technologies
(formerly IBM Endicott). Dr. Das has 20 years of experience in microelectronics packaging development for
applications ranging from HPC to medical to quantum electronics. He holds 48 patents and more than 115
publications. Email Rabindra.Das@ll.MIT.edu

Jason Plant is a Member of the Associate Staff in the Advanced Technology Division of MIT Lincoln
Laboratory, Lexington, MA. He is responsible for developing advanced compound-semiconductor optoelectronic components
including the development and hybrid integration of high-power semiconductor lasers, optical amplifiers, photodetectors and
optical modulators with silicon nitride based photonic integrated circuits (PICs).

22 Chip Scale Review January • February • 2024 [ChipScaleReview.com]
22