Page 15 - Chip Scale Review_January-February_2024-digital

Heterogeneous chiplet integration to make megachips

By Rabindra N. Das, Jason Plant, Alex Wynn, Matthew Ricci, Ryan Johnson, Matthew Stamplis, et al. [MIT Lincoln Laboratory]
T h i s p a p e r d e s c r i b e s a used to fabricate megachip modules. chip-to-chip spacing to minimize the

new, extremely large area
of megachip buildup layers having
integrated circuit (ELAIC) The present process allows fabrication interconnect length, on-chip memory,
higher bandwidth connections, and
solution—we are calling a “megachip”— thicknesses in the range of 1-10µm, which management for greater heat densities,
su it able for combi n i ng mu lt iple allows packaging structures having while being pushed into higher I/O
chiplets of varying type (e.g., memory, both finer pitch and higher density. The counts, smaller pitches, and larger
application-specific integrated circuits processes and materials used to achieve footprints [5-6]. This necessarily
[ASICs], central processing units [CPUs], smaller feature dimensions, satisfy drives a requirement for improving the
graphics processing units [GPUs], power stringent registration requirements, and power efficiency of the chip-to-chip
conditioning) into a single package on a achieve robust electrical interconnections I /Os. In addition, new advanced
common interconnect platform. are discussed. packaging requires low-loss, mixed
The megachip approach helps to material, and versatile construction
rearchitect heterogeneous chip tiling Introduction to accom mod ate t he complex it y
for developing highly complex systems The increasing demand for digital associated with size, weight, and
having desired circuit density and computing, mobility, and connectivity power (SWaP) optimization.
performance. Recent work on large- i s d r iv i ng t he m ic r o ele c t r on ics Conve nt ion al ly, bet t e r w i r i ng
area superconducti ng i nteg rated industry toward cost-driven, highly- densities have been achieved by
circuits to join multiple individual integrated, miniaturized technology using filled dielectric to reduce via
die is highlighted in this article, with increased performance and lower di mensions, li nes, a nd spaces —
with particular attention paid to the power consumption to bring next- t h e r e b y i n c r e a s i n g t h e n u m b e r
processing of the high-density electrical generation devices into more and more of ci rcu it laye r s — a nd ut i l i z i ng
interconnects formed between the applications [1-2]. Over the last decade, m i cr ov i a s fo r i n t er c o n n ec t io n .
individual die. A variety of megachip high-performance computing (HPC) However, each of these methods has
a s se mbl ie s we r e fabr icat e d a nd has evolved to adapt smaller and more inherent limitations. For example,
characterized using several techniques diverse technology nodes suitable for there are limitations related to laser
(i.e., scanning-electron microscopy artificial intelligence (AI), machine drilling and electroplating of high
(SEM), optical microscopy, confocal learning, and embedded computing aspect ratio blind- and through-vias,
microscopy, X-ray) to investigate the p l a t f or m s — t h e s e a p p l i c a t i on s increased resistance of narrow (and)
integration quality, minimum feature consistently involve trade-offs between long circuit lines, and increased cost
size, silicon content, die-to-die spacing, enabling more compute capability of fabrication related to additional
and gap f illing. Silicon dioxide, versus constraints in volume, weight, w i r i ng l a ye r s [7 ]. A s a r e s u l t ,
ben zocyclobutene (BCB), epoxy, power, and thermal management. microelectronics packaging is moving
polyimide, and silicone-based dielectrics Most of the power consumption toward alternative, innovative, low-
were used for gap fill, via formation and for the above applications is due cost approaches as solutions for
redistribution layers (RDLs). to moving data between chips in miniaturization [8-10]. Fabrication,
For the megachip approach, the a syst e m r at he r t h a n t he a ct u al a s s e m b l y, a n d h e t e r o g e n e ou s
thermal stability is improved by reducing c om p ut i n g [ 3 ] . F u r t he r mo r e , integration are bridging the gap by
the die-to-die (D2D) gap and increasing traditional Moore’s Law scaling for enabling economic use of the third
the silicon content, allowing assemblers developing next-generation devices dimension (2.5D and 3D packaging).
to mitigate the problem of mismatch faces various challenges including System-level i nteg rat ion is also
in coefficient of thermal expansion fabr icat ion of la rge r ch ip si z e s emerging. These approaches include
(CTE) for different substrates/modules and associated yield improvement, multi- die system- on- chip (SoC),
integration schemes, which is important development time, and cost scaling. system-in-package (SiP), stacked die,
for allowing the broad temperature range This has forced the microelectronics or package-stacking solutions.
stability from reflow to operation at indust r y to develop a number of In addition to the trend toward
room or even cryogenic temperatures. alt e r nat ive a dva nce d pa ck ag i ng miniaturization, new materials and
Megachip tech nolog y facilit ates architect u res and heterogeneous structures are required to keep pace
more space-efficient designs and can i nt eg r a t io n t e ch nolog ie s [4]. A with more demanding packaging
accommodate most heterogeneous modern packaging architecture needs performance requirements. Wafer-
dies without compromising stability or to integrate multiple processor and level packages (WLP), panel-level
introducing CTE mismatch or warpage. accelerator chips with minimu m packages ( PLP), silicon /orga n ic
A variety of heterogeneous chips were i nt e r p o s e r s w it h r e d i s t r i bu t io n

13
Chip Scale Review January • February • 2024 [ChipScaleReview.com] 13