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Vecchio GPU with 11 EMIBs in 2022. Sapphire Rapids [8] IBM’s Direct Bonded Heterogeneous Integration (DBHi)
is the next-generation of Intel’s Xeon® scalable processor. During IEEE/ECTC 2021 and 2022, IBM presented
It consists of four SoCs and they are connected with 10 seven papers on “Direct Bonded Heterogeneous Integration
EMIBs. There are another four EMIBs that connect the (DBHi) Si Bridge” [9-15] (Figure 4). The major differences
four SoCs and the four HBMs (Figure 3). Lately, Intel has between Intel’s EMIB and IBM’s DBHi are as follows: a)
been discussing reducing the number of SoCs to two and Intel’s EMIB has two different bumps (C4 and C2) on the
shipping a new iteration of the product by the end of 2023 chiplets (and there are no bumps on the bridge) (Figure 2),
or early 2024. while IBM’s DBHi has C4 bumps on the chiplets and C2
bumps on the bridge (Figure 3); and b) Intel’s EMIB has
the bridge embedded in the cavity of a build-up substrate
with a die-attach material and then laminated with another
build-up layer on top, while IBM’s DBHi has a substrate
that is just a regular build-up substrate with a cavity on top
as shown in Figure 4.
The bonding assembly process of DBHi is very simple
(Figure 4). First, nonconductive paste (NCP) is applied
on Chip 1. Then, Chip 1 and the bridge are bonded using
thermocompression bonding (TCB). After bonding, the
NCP becomes the underfill between Chip 1 and the bridge.
NCP is then applied on the bridge and Chip 2 and the
bridge are bonded with TCB. Those steps are followed
by placing the module (Chip 1 + bridge + Chip 2) on the
organic substrate with a cavity and then going through the
standard flip-chip reflow assembly process.
During IEEE/ECTC 2023, IBM presented a paper
on “Direct Bonded Heterogeneous Integration (DBHi):
Surface bridge approach for die tiling” [16]. The authors
demonstrated that the cavity of a build-up package
substrate is not necessary for their Si bridge technology as
shown in Figure 5

AMD’s Instinct™ MI250X compute accelerator
The AMD Instinct™ MI250X compute accelerator is
shown in Figure 6. It can be seen that there are two GPUs
(the second-generation matrix cores for HPC driven by AI)
with each having a size of 790mm . Each GPU is connected to
2
four HBM2E with Si bridges on microbumps. The GPU and
the HBM2E are supported by a build-up package substrate
without any cavity.

Apple’s UltraFusion
UltraFusion is Apple’s innovative packaging architecture
that interconnects the die of two M1 Max chips to create
a SoC with unprecedented levels of stunningly compact
design, extensive connectivity, performance and capabilities.
This architecture doesn’t combine two M1 Max dies into
a single chip package—it also makes the two dies present
themselves as a single chip. The interconnection between
the two M1 Max dies is by a “silicon bridge” as shown in
Figure 7. The chiplets and the Si-bridge are supported by an
ordinary build-up package substrate without any cavity.

TSMC’s local silicon interconnect (LSI)
During IEEE/ECTC 2023, TSMC published two papers
on replacing its CoWoS® by Si-bridge embedded in epoxy
molding compound (EMC) with fan-out RDLs [17,18].
The key reason for this technology is to deal with the
manufacturing yield loss of the ever-increasing size of
the TSV-interposer—the yield loss is so high that the cost
becomes unbearable. Just look at two examples: TSMC
Figure 3: Intel’s Sapphire Rapids with four SoCs and 14 EMIBs [8].

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40 Chip Scale Review November • December • 2023 [ChipScaleReview.com]