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Figure 2: Main design challenges for high-end probe cards for HPC applications and the development process flow.
f inal hardware deployed in high- definition can lead to a high rate th rough a higher nu mber of test
volume manufacturing (HVM) product of false negatives and result in the insertions before being f lagged as
testing. These discrepancies will have scrapping of good dies or result in failed. In the worst-case scenario, an
a negative impact on product binning more re-screen testing to compensate underperforming die may escape the
and per for mance t u ni ng thereby for the yield loss. Furthermore, such tests and result in a possible return
leading to a deviation in speed binning incorrect product definitions can also materials authorization (RMA) request
results and can lead to a product lead to a high rate of false positive (from the field) in the future.
definition that is not optimized. An test results that increase the cost of T he obje c t ive of t h i s wor k i s
incorrect or compromised product test because the die may have gone to docu ment t he desig n process

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30 Chip Scale Review November • December • 2023 [ChipScaleReview.com]