Page 14 - Chip Scale Review_September-October_2023-digital

Improving wafer test efficiency and minimizing cost per die

By Luca Fanelli [SPEA America]

T he ever-growing electronics cue when designing silicon wafer layouts In the past, we used to have a silicon

d e m a n d fo r i n c r e a si n g
such as triangular dies, greatly elongated
performance and functionality, (Figure 1). Certain non-square dies, substrate, on top of which we had the
silicon structure of the die. However,
and for reducing system form factor, rectangular dies, parallelogram dies, it’s not uncommon today to have 3D
power and cost at the same time, is trapezoidal dies, L-shaped dies, and the structures that include dies on both sides
driving the rollout of innovative chip like, are able to be laid out in the area of the silicon with exposed pads on the
architectures. New semiconductor of a circular semiconductor wafer more top and the bottom. In other cases, the
materials, alternative pad designs, and efficiently than square dies. Further, a dies are made of multiple layers covering
ever-shrinking geometries are raising peripheral area of these certain non- the entire vertical structure, so that we
the complexity and the cost of wafer test, square dies is advantageously increased have a single die with access from the
posing tough challenges—especially on relative to the area contained within top and the bottom. Applications like
the probing side. These trends are driving the peripheral area to accommodate microelectromechanical systems (MEMS)
the need for innovative test techniques increased I/O connections to the active require such multi-layer structures
able to increase capacity and control elements of the die. in order to achieve the mechanical
capital equipment cost. This article In addition to varied die geometries, functionality of the device (Figure 2).
surveys the trends impacting wafer test multi-project wafers (MPW) are also T he fabr icat ion of ve r t ical ly-
today and the industry’s response to these often used, especially in the case of low- interconnected multilayer stacks is
challenges. In particular, a new approach to mid-volume production runs. They enabled by specific wafer bonding
to wafer testing, based on multiple flying amalgamate different chip designs—with techniques and can use silicon-top-silicon
probe cards, has been introduced in order different shapes—on the same silicon layers or varied materials, such as glass
to allow manufacturers to increase test wafer, thereby amortizing the wafer (Figure 3). The advantages offered in
efficiency, thereby minimizing the cost fabrication costs across many designs, terms of performance, form factor, and
per die. teams, and users. integration, are fueling the spread of
Optimizing on a vertical level. As both double-sided wafers with single side
Efficient use of the silicon surface the form factor of chips is continuing to dies, and double-sided wafers with pass-
The need to reduce costs and maximize shrink, while the demand for increased through dies.
yield often calls for a more efficient use of connectivity and functionality shows an
the semiconductor silicon, both on a planar unabated rising trend, the adoption of Impact on the testing process
level and on a vertical level. The following technologies that require 3D approaches As we have seen, non-square dies,
sections discuss these two levels. for the integration of devices and system non-regular geometries in the wafer
Efficient use at the planar level. On design is growing. In particular, for layout, and MPWs are all ways to
the planar level, varied wafer layout some complex applications (e.g., we use the semiconductor wafer area
geometries, differing from the traditional can think about miniaturized medical in the most efficient way. Besides
squared-based dies, are seeing wider devices requiring multiple functions to having advantages with respect to
adoption. To understand how geometry be squeezed into the size of an ingestible manufacturing costs, they also have
can be used to maximize a surface area pill), a vertical silicon optimization an impact on manufacturing and test
utilization, we can take our starting point allows higher packing densities as well as processes, posing enormous challenges
from one of the world’s most famous shorter chip-to-chip interconnects. on the probing and test side.
graphic artists: Maurits Cornelis Escher.
Born at the end of the 19th century, this
mathematically-inspired genius has
made wide use of a technique called
“tessellation” that involves the covering
of a plane surface by repeating over and
over again a shape, without any gaps or
overlaps. The shape itself can be more
or less complex, as long as its repetitions
on the plane can intersect perfectly,
without leaving any gaps. Other than
creating beautiful and visionary images,
a similar technique can also be used as a
Figure 1: Geometry designs that maximize a surface area utilization can be seen.

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12 Chip Scale Review September • October • 2023 [ChipScaleReview.com]