Page 12 - Chip Scale Review_September-October_2023-digital

[1], split as follows: flip-chip with 51% solutions such as WLCSP, SiP, and bonding ensures a robust and reliable
market share, followed by 2.5D/3D with he t er oge ne ou s i nt eg r at io n ( H I ) connection between chiplets, enhancing
21% of the market—and expected to be the technologies. Samsung uses its fan-out their integration within the advanced
fastest-growing AP platform by 2028. SiP panel-level packaging (FOPLP), flip-chip, packaging platform. This technology
is estimated at 19% market share, followed wire bond, and 3D stacking packaging has unlocked new possibilities in
by WLCSP and FO packaging with 5% capabilities to package its accelerated semiconductor design, enabling the
and 4% market share, respectively. processing units (APUs) and memory, but development of cutting-edge solutions
Among the key players, outsourced it also outsources production to companies that were once considered impossible.
semiconductor assembly and test (OSAT) like ASE, Amkor, and PTI. Samsung has Hybrid bonding is a cutting-edge
companies and major integrated device also started manufacturing FOPLP for technology that enables diverse chip
manufacturers (IDM) and foundries, such Google’s Tensor G2 and Baidu’s I-CubeS. architectures, catering to high-end
as TSMC, Intel, and Samsung, are heavily applications like HPC, AI, servers,
investing in high-end packaging solutions, HI and chiplets: Revolutionizing AP and data centers. As the technology
with a focus on 2.5D/3D stacked packaging. roadmaps matures, it is expected to expand further
As an IDM, Intel has been actively HI and chiplets represent a paradigm into consumer applications, memory
investing in AP technologies. Intel utilizes shift in semiconductor design and devices, and mobile and automotive
AP techniques such as its Embedded packaging. The HI concept involves applications, benefiting from high-
Multi-die Interconnect Bridge (EMIB) c o m bi n i n g d i f fe r e n t m a t e r i a l s , performance die-to-die connections.
and Foveros for its products and offers processes, and devices to create The concept of HI is driving innovation
customers foundry and packaging a u nif ied system. This approach in packaging technologies to meet
services. The company’s strong emphasis allows for the seamless integration specific performance, size, power
on innovation and vertical integration of diverse f unctional chiplets on consumption, and cost requirements.
positions it as a significant player in the a single package, unlocking new Hybrid bonding emerges as a feasible
AP arena. possibilities in semiconductor design pathway for high-end HI applications,
TSMC, a global leader in semiconductor and manufacturing. with tiny copper pads embedded in
foundries, offers AP services through Chiplets, on the other hand, are a dielectric, forming both dielectric-to-
its 3DFabric™ platform, featuring fundamental aspect of HI. According dielectric and metal-to-metal bonds.
technologies like Integrated Fan-Out to our definition at Yole, the chiplet This bonding technology provides
(InFO), chip-on-wafer-on-substrate approach represents an emerging n u m e r o u s a d v a n t a g e s , s u c h a s
®
(CoWoS ) and 3D System-on-Integrated- semiconductor design philosophy significantly increased I/O connections,
®
Chip (TSMC-SoIC ). The company that combines two or more discrete m i n i mal sig nal delay, expa nded
provides a comprehensive wafer-to- dies in a disaggregated SiP design. bandwidth, higher memory density, and
packaging solution, covering wafer front- Chiplets offer more design flexibility, improved power and speed efficiencies.
end manufacturing, wafer-level processes, faster time to market, better yield, T h e A P t e c h n o l o g y r o a d m a p
packaging, and on-substrate assembly. and economic benefits over possible illustrated in Figure 3 presents an
Collaborating with packaging companies monolithic alternatives. The functions intriguing progression of miniaturization
such as ASE, SPIL, and Amkor, TSMC of ch iplet s e ncompa ss esse nt ial and increasing density in four key
has solidified its position as a dominant intellectual property (IP) blocks found elements: 3D stack pitch, bump I/O pitch,
player in the AP market. in typical processor SoCs, including RDL line/space, and ball I/O pitch over a
Being the world’s largest OSAT, ASE cent ral processing units (CPUs), decade. The 3D stack pitch highlights a
specializes in AP technologies, including graphics processing units (GPUs), clear trend toward miniaturization across
flip-chip, fan-out, and SiP solutions. The neural processing units (NPUs), I/Os hybrid bonding methods: wafer-to-wafer,
company’s collaborations with Intel, and memory controllers and interfaces, die-to-wafer, and die-to-die. With wafer-
TSMC, and other leading semiconductor cache memory, and analog functions to-wafer, we observe an impressive
companies underscore its crucial role in (SerDes, PLLs, DAC, ADC, PHYs, etc.). reduction from 2µm in 2019 to a
driving advancements in AP technologies. projected 0.8µm–0.5µm by 2029. This
Amkor, a significant player in the Hybrid bonding: Bridging the represents a significant achievement in
semiconductor packaging and testing gap in HI reducing pitch size, which might enable
industry, offers a diverse range of AP H y b r i d b o n d i n g i s a n o v e l the integration of more components and
solutions. These include wafer-level technology that enables the vertical potentially enhance performance.
packaging (WLP), 2.5D/3D packaging, stacking of semiconductor devices, Similarly, die-to-wafer hybrid bonding
flip-chip, and SiP solutions. Amkor potentially significantly boosting is expected to shrink from 10µm in
remains a key contender in the rapidly device performance, functionality, and 2022, to 6–4.5µm by 2029. This also
evolving advanced packaging market with reliability. It is a critical enabler in suggests a push towards higher-density
a broad portfolio of AP offerings. HI, offering exceptional precision and packaging, which can lead to smaller,
As an IDM, Samsung has a strong reliability in the bonding process. Hybrid more efficient devices. However, the
presence in the AP market offering reduction rate in pitch size appears

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