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unconverted functional test content on
the ATE; 2) ATE hardware that supports
high-speed I/O (HSIO) communication;
3) enhanced functional coverage closure
using constraint random test content; 4) a
native software debugging environment
instead of vector-pattern compare and
error reporting; 5) or an enhanced PSS
scenario analysis to observe how varying
test conditions impact PSV.

PSS implementation
A joint cooperative initiative between
Cadence and Advantest involved a
combination of the PSS and HSIO
approaches. The companies have
developed a solution that involves
PSS-based test content creation, an
interface to ATE software, the loading
of parameterized test content, test
execution on ATE hardware, and debug
and analysis (Figure 2). The solution
begins with the Cadence Perspec
System Verifier, which automates the
process of extending the PSS models
used in pre-silicon validation to
Figure 1: Six EX Test Stations with M4127 handlers fitting within a 5m by 5.5m laboratory space to speed up the ATE environment, reducing the
test-pattern validation and other engineering tasks. complex use-case scenario development
time. A container file labeled FDAT in
Accordingly, there is a trend for an intellectual property (IP) standards, Figure 2 provides an efficient interface
increasing amount of functional tests. has promulgated the Portable Test and between Perspec and the Advantest
The challenges involved in creating Stimulus Standard (PSS), which specifies SmarTest 8 software for its V93000
f u n c t i o n a l t e s t o n AT E c a n b e a single representation of stimulus and ATE systems.
summarized in two major categories. test scenarios that span simulation,
First, the need to convert the functional emulation, and post-silicon [2].
test content into a production test Interacting natively with DUT with
vector pattern requires tooling and Linking the EDA and ATE no cyclization
extensive development time. Second, communities Continuing with the process noted
on a typical ATE, there is no native A result of PSS is that the once- in the previous section, Advantest’s
software debugging environment, siloed disciplines of the EDA and new Lin k Scale ATE inst r u ment
making it very difficult for the test ATE communities can work together. interacts natively with the DUT using
case developer to debug any issues Barriers remain, however. Structural low pin-count HSIO, such as USB
i n suppor t of t he t est e ng i nee r. test dominates the ATE side, but and PCI Express interfaces running
Excessively long, unpredictable debug rising quality expectations are driving in full-protocol mode, without pattern
cycles are inevitable. That is where a need for more functional test to cyclization. Collected test traces can
pre-silicon methodologies and an ensure the chip will perform properly be viewed in a SmarTest viewer or
ATE instrument can work together to in its end application environment or imported into Cadence’s Verisium
seamlessly and interactively validate mission mode. However, as previously Debug AI-powered debug tool for
the functional test content to help to mentioned, converting functional test correlation with the original PSS
meet these challenges. content into production test vectors tests. In addition, Link Scale can host
embedded software debuggers such as
requires extensive development time, the Lauterbach TRACE32.
Introducing the PSS standard and a typical ATE system lacks a native
The transition from the pre-silicon software debugging environment that
verification stage to first silicon— could speed up the process [3]. Device validation best practices
involving bring-up, bare-metal test The process outlined in Figure 2 can
execution, and the ATE stage—can be Proposed solutions to handling significantly ease the burden of the post-
greatly smoothed through the reuse of functional test content silicon activities but not eliminate it.
pre-silicon verification test content. A solution would involve meeting one Not all DUTs will have HSIO channels
To that end, the Accellera Systems or more of the following requirements: for the delivery of test patterns without
Initiative, an organization focused on 1) seamless software-driven execution of the necessity of converting them to
the creation and adoption of EDA and cyclized test vectors, or not all functions

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