Page 38 - Chip Scale Review_July August_2023-digital

I/O drivers on the interposer are scaled but this is nothing like what can be This stacking tech nolog y allows
like those within an SoC. Interposers done today. Directly bonding layers sturdy physical assembly and seamless
can be made of either silicon or glass; of circuitry and integrating them vertical interconnect with almost no
glass reduces parasitics to achieve even with ultra-short vertical interconnect capacitance. Hybrid bonding provides
greater returns. drastically reduces the wire for faster, thousands to millions of ultra-short
Our toolbox also has 3D assembly. lower power devices. wires between layers of ultrathin full
Chips have been stacked for years with Hybrid bonding is a vital tool in our chips or chiplets, with wiring pitches of
cascading waterfalls of wire bonds, box for either 2.5D or 3D assembly. just a few microns—rivaling the global
interconnect of today’s leading SoCs.
A major power tool in the box is
heterogeneous integration. 2.5D and 3D
®
assembly allow our “LEGO blocks”
to be built in a vast array of materials,
at different nodes, and in dissimilar
process flows. The disparate pieces can
nonetheless be assembled as tightly
as any components in an SoC. What’s
more, f ine-grained wiring allows
assembly of completely incompatible
semiconductor technologies that could
never be combined in an SoC at any
cost. Heterogeneous integration allows
assemblies to incorporate only best-
of-class components, boosting system-
level per for mance 100 0x al most
instantaneously.
Dozens of other tools crowd our
toolbox, including:

• Adding back-end-of-line (BEOL)
memory (e.g., magnetoresistive
random access memory [MRAM])
through additive semiconductor
manufacturing;
• Adding magnetics for local precise
high-efficiency power delivery;
• Adding thermal materials, sensor
materials, etc.;
• Building optical interconnect into
interposers;
• Integrating analog components;
• Incorporating custom chiplets; and
• Applying non-standard processes.
An intriguing possibility is the
revival of the Sea of Gates. This
c once pt i m ag i ne s bu i ld i ng va st
arrays of undifferentiated transistors.
Functionality is not built in with the
transistors, but created by the wiring
layers in the BEOL. Manufacturing the
transistor layers would be extremely
efficient, as all dies would be completely
identical—only the BEOL would differ.
This promising idea fell by the wayside
with the dominant rise of the SoC. A
Sea of Gates incorporates nothing but

36 Chip Scale Review July • August • 2023 [ChipScaleReview.com]
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