Page 39 - Chip Scale Review_July August_2023-digital

digital transistors; an SoC contains manufacturing. Importantly, they would be economically feasible to develop
memory, modems, and analog and not compete with the industry giants at all. new devices; risk taking will again
mixed-signal elements. SoC flexibility A modest BEOL and advanced packaging become possible and startups will be
overpowered the elegant Sea of Gates fab could cooperate under nondisclosure created for millions, or at most a few
approach. But now, in chiplet designs, agreements (NDAs) with big foundries tens of millions. Innovation looks bright
digital transistors can once again be that compete fiercely with one another. again under Foundry 2.0. Perhaps a new
conveniently separated from all other As an utterly neutral party, the smaller “Golden Age” is on the horizon.
components. High-volume foundries fab would enable assemblies that are truly
could manufacture immense numbers heterogeneous in every sense, assembling Biography
of identical Sea of Gates chiplets to be chips or chiplets from multiple sources. Robert (Bob) Patti is President of
differentiated by wiring. NHanced Semiconductors in Batavia,
Summary Illinois. He helped design over 100 chips
Let’s talk about money In summary, innovation has been at his first semiconductor startup, ASIC
While the gains in power, size, and stifled by the high cost risk of developing Designs, and later founded Tezzaron
performance are exciting and may be SOTA SoCs. New semiconductor Semiconductor to develop 3D wafer
compelling enough in many applications, startups have virtually disappeared stacking. His latest company, NHanced
the elephant in the room is cost. Foundry because a first-try product requires Semiconductors, looks to drive the
2.0 must provide a fundamental cost hundreds of millions of dollars. In rise of Foundry 2.0. Bob received the
benefit to the end consumer. this high-stakes game, investors are 2009 SEMI Award for North America
Today’s massive SoCs can cost unwilling to fund anything but slam- for his pioneering work in 3D IC
hundreds of millions to design. The dunk investment unicorns. Foundry integration as well as the 2015 3DIncites
factor ies that manufact u re them 2.0 changes all of this. With chiplets, I nd iv idu al Ach ieve me nt Awa rd.
are measured in tens of billions. By advanced packaging, and additive Email rpatti@NHanced-semi.com
comparison, Foundry 2.0 technologies semiconductor manufacturing, it will
generally run in the ~1µm range—
a more forgiving node. Development
nonrecurring engineering (NRE) costs
are likely to be measured in hundreds of
thousands of dollars. The leading edge of
high-speed, high-volume manufacturing
is just now catching up to the chiplet
revolution; as it gains traction it will
drive costs far down, enabling affordable
mass market opportunities for chiplet-
based semiconductor devices.

The new opportunity
Foundry 2.0 gives leading-edge
fabs a valuable point of entry to niche
markets that are currently untapped. By
disaggregating their powerful SoCs into
chiplets, fabs will create state-of-the-art
components that customers will eagerly
incorporate into their assemblies. Foundry
1.0 will thereby participate fully in
Foundry 2.0, penetrating lucrative custom
markets without disrupting the high-
volume business model.
A new niche opens for smaller fabs
that do not build any transistors, but
focus on the value-added technologies
discussed here. These factories would be
10-100x less expensive to build and equip E-Tec Interconnect AG, Mr. Pablo Rodriguez, Lengnau Switzerland
than high-volume transistor factories. Phone : +41 32 654 15 50, E-mail: p.rodriguez@e-tec.com
Their business model would target high-
mix, high-touch, low- to mid-volume

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