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requires that customers shoe-horn big field-programmable gate
arrays (FPGAs) or multi-function SoCs into their applications.
These one-size-fits-all chips provide workable solutions, but they
typically contain millions of transistors that the application doesn’t
need and never uses. They take up more space, consume more
power, and run more slowly than a sleek, well-tuned custom chip.
Today, IC development costs range into the billions. Developers
are scarce and are increasingly averse to risks in technology,
design, or market. Innovation is always risky, and is therefore
highly constrained in this environment. Customization is nearly
impossible; diverting precious resources to address a niche
customer carries an enormous opportunity cost that no leading-
edge fab is willing to accept. We are at the end of the road for the
semiconductor business model driven by Moore’s Law.
Of course, the existing Foundry 1.0 model is extremely efficient
and effective. It runs uniform, well-proven processes and produces
vast numbers of identical devices with tremendous economies of
scale. It seems highly unlikely that a technology breakthrough will
fundamentally alter this model. The best answer is to not change the
reliable and successful Foundry 1.0 model, but to build upon it.

Fostering a resurgence:
Foundry 2.0
The Foundry 2.0 model aims to stimulate innovation via
advanced packaging and additive semiconductor manufacturing,
using current semiconductor production as feedstock. Under
Foundry 2.0, the existing semiconductor plants will use their
formidable production model to build chiplets—disaggregated
®
“LEGO blocks” of today’s existing SoCs—while new, smaller
fabs perform additional cleanroom processing on these chiplets
to produce low- to mid-volumes of finished devices.
Just as SoC benefits came from eliminating chip-to-chip
wiring, Foundry 2.0 will use advanced packaging to reduce
chiplet-to-chiplet wiring. Advanced packaging interconnect
(wire) is as good as, or even better than, wiring within a modern
SoC; this breaks the chip-to-chip wiring barrier. Combining
separately manufactured chiplets frees us from the tyranny of
forcing everything into one chip and one fabrication flow. The
®
“LEGO blocks” that were combined in an SoC can be taken
apart again and selectively assembled in various advanced
packages. New combinations of blocks are possible. Non-
essential blocks are simply left out. Lean, swift, single-function
chiplets are wired together into flexible, cost-effective solutions.
This changes everything—a new era of semiconductors is born.
Foundry 2.0 is best viewed as a toolbox of technologies
and processes to integrate chiplets and create customization
by adding materials or unique processes on top of Foundry
1.0 produced dies or wafers. One tool in the toolbox is 2.5D
assembly—perhaps the worst term the industry ever coined.
This is side-by-side chiplet assembly on an interposer. State-
of-the-art (SOTA) chiplet assembly permits high-speed pick
and place of components with sub-micron accuracy onto
interposers—the equivalent of yesterday’s circuit boards.
Interposers provide micron or sub-micron wiring. Because all
the wiring is essentially on-chip, ESD structures drastically
shrink or altogether disappear. Similarly, the chiplet-to-chiplet

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