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GUEST EDITORIAL

Foundry 2.0: A renaissance in innovation

By Bob Patti [NHanced Semiconductors]

O ur society craves customization. startup company could develop a new more transistors per die. Cell phones

We all want clothing, cars,
now routinely outperform the personal
chip and go to market for 10 or 20 million
and phones that fit us and
this progression was bundling ever larger
our personal usage styles. dollars. New devices and intellectual computers (PCs) of the 1990s. Key to
property (IP) thrived in the market.
In semiconductor hardware, however, Individual companies developed and groups of functions into system on chip
customization has become prohibitive. tuned their own semiconductor products. (SoC) devices to reduce cost, power,
How did the industry get here? What can Moore’s Law was in full swing and and size. These improvements were
be done to revive innovation in high- roomfuls of 1970s electronics became largely enabled by reduction in wire size
end chips? This article discusses a new desktops, laptops, tablets, and personal and length. Cumbersome chip-to-chip
business model called Foundry 2.0. digital assistants (PDAs). wiring and electrostatic discharge (ESD)
structures were replaced by elegant on-
Remembering the “Golden Age” The rise of the SoC chip communication. Today’s one-size-
The 1980s and 1990s saw a golden era Since the “Golden Age,” transistors fits-all SoCs are the result.
of custom integrated circuits (ICs). New have shrunk from 1µm to 2nm while However, prog ress on the path
gate arrays, or even standard cell custom wafers grew from 200mm to 300mm, described above has slowed to a crawl.
devices, were relatively inexpensive. A providing more dies per wafer and vastly Absorbing more features into an SoC
no longer translates reliably into cost,
power, and size improvements. Why?
Because advances in wiring have fallen
far behind advances in transistors.
Wiring limitations are imposed by
the limits of process technology and
by basic physics. Today’s wires are too
small to be made with smooth edges; the
structures look as if they were drawn
with a crayon. Electrons bounce and
scatter off these ragged edges, seriously
impacting signal speed. At the same
time, scaling draws wires closer together
and they become more resistive. Wire
proximity also adds to capacitance and,
therefore, energy consumption. For all of
these reasons, wires consume most of the
power and most of the delay at very small
nodes; transistors take a tiny portion of
both budgets. Wires are the root of the
problem with continued scaling.
The current business model:
Foundry 1.0
As feat u re si zes have sh r u n k ,
development and factory costs have risen
to staggering heights. Stark economic
realities force today’s fabs to echo Henry
Ford’s famous quote, “Any color the
customer wants, as long as it is black.”
Certainly, software provides a level of
customization, but hardware inflexibility

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